參數(shù)資料
型號(hào): XR17D152
廠商: Exar Corporation
英文描述: UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
中文描述: 通用(3.3V和5V)PCI總線的雙UART
文件頁(yè)數(shù): 55/68頁(yè)
文件大?。?/td> 772K
代理商: XR17D152
á
REV. 1.2.0
XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
55
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V VCC = 3.0-5.5V)
TA=0
o
to
70
o
C (-40
o
to +85
o
C for industrial grade package).
S
YMBOL
P
ARAMETER
M
IN
M
AX
U
NITS
N
OTES
XTAL1
XTAL2
Crystal Frequency
24
MHz
On-chip osc.
ECLK
External Clock
33
MHz
VCC = 3.3V ±10%
50
MHz
VCC = 5V ±10%
T
ECLK
External Clock Period
(T
ECLK
= 1/ECLK)
30
ns
VCC = 3.3V ±10%
20
ns
VCC = 5V ±10%
T
ECH,
T
ECL
External Clock High/Low
Time
13
ns
VCC = 3.3V ±10%
8
ns
VCC = 5V ±10%
I
OH(AC)
Switching Current High
-12VIO
mA
See PCI Specification
Rev. 2.3
I
OL(AC)
Switching Current Low
16VIO
mA
See PCI Specification
Rev. 2.3
I
CH
High Clamp Current
25+(Vin-VIO-1)/0.015
mA
VIO+4 > Vin
VIO+1
I
CL
Low Clamp Current
-25+(Vin+1)/0.015
mA
-3 < Vin
-1
Slew
R
Output Rise Slew Rate
1
4
V/ns
0.2VIO - 0.6VIO load
Slew
F
Output Fall Slew Rate
1
4
V/ns
0.6VIO - 0.2VIO load
T
CYC
CLK Cycle Time
30
ns
PCI Bus Clock, CLK
T
HI
CLK High Time
11
ns
T
LO
CLK Low Time
11
ns
CLK Slew Rate
1
4
V/ns
T
VAL
CLK to Signal Valid Delay
2
11
ns
T
ON
Float to Active Delay
2
ns
T
OFF
Active to Float Delay
28
ns
T
SETUP
Input Setup Time to CLK -
bused signals
7
ns
T
HOLD
Input Hold Time from CLK
0
ns
T
PRST
RST# Active Time After
Power Stable
1
ms
T
CRST#
RST# Active Time After CLK
Stable
100
us
RST# Slew Rate
50
mV/ns
相關(guān)PDF資料
PDF描述
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