
XR17D152
REV. 1.2.0
á
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
F
EATURES
.....................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
............................................................................................................................................................. 1
F
IGURE
2. P
IN
O
UT
OF
THE
XR17D152 ........................................................................................................................................... 2
ORDERING
INFORMATION
.................................................................................................................................2
P
IN
D
ESCRIPTIONS
.........................................................................................................................................3
PCI LOCAL BUS INTERFACE.....................................................................................................................3
MODEM OR SERIAL I/O INTERFACE........................................................................................................3
ANCILLARY SIGNALS.................................................................................................................................4
FUNCTIONAL DESCRIPTION ...........................................................................................6
PCI Local Bus Interface...............................................................................................................................................6
PCI Local Bus Configuration Space
Registers............................................................................................................6
EEPROM Interface......................................................................................................................................................6
1.0 APPLICATION EXAMPLES ...................................................................................................................7
F
IGURE
3. T
YPICAL
A
PPLICATION
FOR
A
U
NIVERSAL
A
DD
-
IN
C
ARD
.................................................................................................... 7
F
IGURE
4. T
YPICAL
A
PPLICATIONS
IN
AN
E
MBEDDED
S
YSTEM
............................................................................................................ 8
2.0 XR17D152 REGISTERS .........................................................................................................................9
F
IGURE
5. T
HE
XR17D152 R
EGISTER
S
ETS
..................................................................................................................................... 9
2.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS .......................................................................... 10
T
ABLE
1: PCI L
OCAL
B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
....................................................................................................... 10
2.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................. 11
T
ABLE
2: XR17D152 D
EVICE
C
ONFIGURATION
R
EGISTERS
............................................................................................................. 12
T
ABLE
3: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
BYTE
ALIGNMENT
................................................................................... 12
T
ABLE
4: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
DWORD
ALIGNMENT
............................................................................... 13
2.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 14
F
IGURE
6. T
HE
G
LOBAL
I
NTERRUPT
R
EGISTER
, INT0, INT1, INT2
AND
INT3.................................................................................. 15
T
ABLE
5: UART C
HANNEL
[1:0] I
NTERRUPT
S
OURCE
E
NCODING
..................................................................................................... 15
T
ABLE
6: UART C
HANNEL
[1:0] I
NTERRUPT
C
LEARING
: .................................................................................................................. 15
2.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
00-00).............................................................................................................................................................................. 16
F
IGURE
7. T
IMER
/C
OUNTER
CIRCUIT
............................................................................................................................................... 16
T
ABLE
7: TIMER CONTROL R
EGISTERS
...................................................................................................................................... 16
2.2.3 8XMODE [7:0] (DEFAULT 0X00)................................................................................................................................ 17
2.2.4 REGA [15:8] RESERVED ........................................................................................................................................... 17
2.2.5 RESET [23:16] - (DEFAULT 0X00)............................................................................................................................. 17
2.2.6 SLEEP [31:24] - (DEFAULT 0X00)............................................................................................................................. 18
2.2.7 DEVICE IDENTIFICATION AND REVISION............................................................................................................... 19
2.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS.............................................................................................................. 19
2.2.10 MPIO REGISTER ...................................................................................................................................................... 19
2.2.8 REGB REGISTER ....................................................................................................................................................... 19
F
IGURE
8. M
ULTIPURPOSE
INPUT
/
OUTPUT
INTERNAL
CIRCUIT
........................................................................................................... 20
3.0 CRYSTAL OSCILLATOR / BUFFER ...................................................................................................22
F
IGURE
9. T
YPICAL
OSCILLATOR
CONNECTIONS
............................................................................................................................... 22
F
IGURE
10. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
........................................................................................ 22
4.0 TRANSMIT AND RECEIVE DATA .......................................................................................................23
4.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS ............................................... 23
4.1.1 NORMAL RX FIFO
DATA UNLOADING AT LOCATIONS 0X100 (CHANNEL 0) AND 0X300 (CHANNEL 1)........ 23
4.1.2 SPECIAL RX FIFO
DATA UNLOADING AT LOCATIONS 0X180 (CHANNEL 0) AND 0X380 (CHANNEL 1)........ 24
4.1.3 TX FIFO
DATA LOADING AT LOCATIONS 0X100 (CHANNEL 0) AND 0X300 (CHANNEL 1).............................. 24
4.2 FIFO
DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN
8-BIT FORMAT ............................................................................................................................................... 25
5.0 UART ....................................................................................................................................................25
5.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 25
T
ABLE
8: T
RANSMIT
AND
R
ECEIVE
D
ATA
R
EGISTER
IN
B
YTE
FORMAT
, 16C550
COMPATIBLE
............................................................ 25
F
IGURE
11. B
AUD
R
ATE
G
ENERATOR
............................................................................................................................................. 26
T
ABLE
9: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
.......................................... 26
5.2 TRANSMITTER ............................................................................................................................................... 27
5.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 27
5.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................. 27