參數(shù)資料
型號(hào): XR17D152CM-0A-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 11/68頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17D152 100TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
á
XR17D152
REV. 1.2.0
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
19
2.2.7
Device Identification and Revision
There are two internal registers that provide device identification and revision, DVID and DREV registers. The
8-bit content in the DVID register provides device identification. A return value of 0x22 from this register
indicates the device is an XR17C152 or an XR17D152. The DREV register returns an 8-bit value of 0x01 for
revision A with 0x02 equals to revision B and so forth. This information is very useful to the software driver for
identifying which device it is communicating with and to keep up with revision changes.
DVID [15:8]
Device identification for the type of UART. The upper nibble indicates it is an XR17Cxxx series device with
lower nibble indicating the number of channels.
Examples:
XR17C158 or XR17D158 = 0x28
XR17C154 or XR17D154 = 0x24
XR17C152 or XR17D152 = 0x22
DREV [7:0]
Revision number of the XR17D152. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB [23:16] (default 0x00)
REGB register provides a control for simultaneous write to both UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data.
2.2.9
Multi-Purpose Inputs and Outputs
The D152 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed to
be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to
generate an interrupt. The outputs can be set to be normal logic 1 or 0 state, or three-state. Their functions and
definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all 8
pins are set for inputs, all 8 interrupts would be or’ed together. The Or’ed interrupt is reported in the channel 0
UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be outputs and to
the three-state condition for signal sharing.
2.2.10
MPIO REGISTER
Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and
monitor the 8 multipurpose inputs and output pins. Figure 8 shows the internal circuitry.
2.2.8
REGB Register
REGB[16] (Read/Write)
Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to both UARTs configuration register.
REGB[19:17]
Reserved.
REGB[20] (Write-Only)
Control the EECK, clock, output (pin 84) on the EEPROM interface.
REGB[21] (Write-Only)
Control the EECS, chips select, output (pin 83) to the EEPROM device.
REGB[22] (Write-Only)
EEDI (pin 82) data input. Write data to the EEPROM device.
REGB[23] (Read-Only)
EEDO (pin 81) data output. Read data from the EEPROM device.
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