參數(shù)資料
型號: XR17D152CM-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 42/68頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17D152 100TQFP
標準包裝: 1
系列: *
á
XR17D152
REV. 1.2.0
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
47
5.8.14
Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bits 0-3 provide single or dual consecutive
character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits. See Table 18 for complete
selections. The XOFF1/XOFF2 characters are transmitted approximately 2 character times after the RX FIFO
level has reached the RX trigger level, irrespective of which trigger table is used (Trigger Tables A-D). The
XON1/XON2 characters are transmitted when the RX FIFO level falls below the next lower trigger level for
Trigger Tables A-C and they are transmitted when the RX FIFO level falls below the (RX trigger level -
hysteresis level) for Trigger Table D. For example, if Trigger Table D is used with an RX trigger level of 56 and a
hysteresis level of 16, the XON1/XON2 characters are sent when the RX FIFO level count falls below 40.
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT-3
FCTR BIT-2
FCTR BIT-1
FCTR BIT-0
RTS/DTR HYSTERESIS
(CHARACTERS)
000
0
000
1
± 4
001
0
± 6
001
1
± 8
010
0
± 8
010
1
± 16
011
0
± 24
011
1
± 32
110
0
± 12
110
1
± 20
111
0
± 28
111
1
± 36
100
0
± 40
100
1
± 44
101
0
± 48
101
1
± 52
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