參數(shù)資料
型號(hào): XR17D152CM-0A-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 22/68頁(yè)
文件大小: 0K
描述: EVAL BOARD FOR XR17D152 100TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
á
XR17D152
REV. 1.2.0
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
29
5.3.2
Receiver Operation in non-FIFO Mode
5.3.3
Receiver Operation with FIFO
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
Re c e iv e Da ta Sh ift
R egister (R S R )
Re c e iv e
D a ta B y te
and E rr o rs
RHR I n te r ru p t (IS R b it -2 )
Re c e iv e Da ta
H o ld ing R egist e r
(RHR)
16X or 8X C lo c k
(8 XM O D E Re g is t e r )
Re c e iv e Da t a Ch a r a c te r s
Da ta Bit
Va lid a t io n
Er ro r
Ta g s in
LS R bits
3:1
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Sampling
Clock (8XMODE Reg.)
E
rror
Tags
(64-sets)
E
rror
Tags
i
n
LS
R
bits
3:1
64 bytes by 11-
bit wide FIFO
Receive Data Characters
FIFO Trigger=48
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Data fills to 56
Data falls to 40
Data Bit
Validation
Receive Data
FIFO
(64-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
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