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XR17D154
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
5
MPIO1
107
I/O
Multi-purpose input/output 1. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO2
74
I/O
Multi-purpose input/output 2. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO3
73
I/O
Multi-purpose input/output 3. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO4
68
I/O
Multi-purpose input/output 4. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO5
67
I/O
Multi-purpose input/output 5. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO6
66
I/O
Multi-purpose input/output 6. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO7
65
I/O
Multi-purpose input/output 7. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
EECK
116
O
Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for
reading the vendor and sub-vendor ID and model number during power up or
reset. However, it can be manually clocked thru the Configuration Register
REGB.
EECS
115
O
Chip select to a EEPROM device like 93C46. It is manually selectable thru
the Configuration Register REGB. Requires a pull-up 4.7K
resistor for
external sensing of EEPROM during power up. See DAN112 for further
details.
EEDI
114
O
Write data to EEPROM device. It is manually accessible thru the Configura-
tion Register REGB. The D154 auto-configuration register interface logic
uses the 16-bit format.
EEDO
113
I
Read data from EEPROM device. It is manually accessible thru the Configu-
ration Register REGB.
XTAL1
110
I
Crystal of up to 24MHz or external clock input of up to 50MHz for data rates
up to 6.25Mbps at 5V and 8X sampling. See AC Characterization table. Cau-
tion: this input is not 5V tolerant at 3.3V.
XTAL2
109
O
Crystal or buffered clock output.
TMRCK
69
I
16-bit timer/counter external clock input.
ENIR
70
I
Infrared mode enable (active high). This pin is sampled during power up, fol-
lowing a hardware reset (RST#) or soft-reset (register RESET). It can be
used to start up all 4 UARTs in the infrared mode. The sampled logic state is
transferred to MCR bit-6 in the UART. Software can override this pin thereaf-
ter and enable or disable it.
TEST#
111
I
Factory Test. Connect to VCC for normal operation.
VCC
64, 90, 112
PWR
5V or 3.3V power supply for the core logic. This power supply determines
the VOH level of the non-PCI bus interface outputs. Note that VCC
≥ VIO for
normal device operation and see
Table 1 for valid combinations of VCC and
equal VIO if sleep mode is used. See Sleep Mode section on page 19. PIN DESCRIPTIONS
NAME
PIN #TYPE
DESCRIPTION