XR17D158
REV. 1.2.1
xr
5V PCI BUS OCTAL UART
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
F
EATURES
.....................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
............................................................................................................................................................. 1
F
IGURE
2. P
IN
O
UT
OF
THE
D
EVICE
.................................................................................................................................................. 2
ORDERING
INFORMATION
.................................................................................................................................2
PIN DESCRIPTIONS ..........................................................................................................3
FUNCTIONAL DESCRIPTION ...........................................................................................8
PCI Local Bus Interface...............................................................................................................................................8
PCI Local Bus Configuration Space
Registers............................................................................................................8
EEPROM Interface......................................................................................................................................................8
1.0 APPLICATION EXAMPLES ...................................................................................................................9
T
ABLE
1: V
ALID
C
OMBINATIONS
OF
VCC
AND
VIO S
UPPLY
V
OLTAGES
.............................................................................................. 9
F
IGURE
3. T
YPICAL
A
PPLICATION
FOR
A
U
NIVERSAL
A
DD
-
IN
C
ARD
.................................................................................................... 9
F
IGURE
4. T
YPICAL
A
PPLICATIONS
IN
AN
E
MBEDDED
S
YSTEM
.......................................................................................................... 10
2.0 XR17D158 REGISTERS .......................................................................................................................11
F
IGURE
5. T
HE
XR17D158 R
EGISTER
S
ETS
................................................................................................................................... 11
2.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS .......................................................................... 11
T
ABLE
2: PCI L
OCAL
B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
....................................................................................................... 12
2.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................. 13
T
ABLE
3: XR17D158 D
EVICE
C
ONFIGURATION
R
EGISTERS
............................................................................................................. 14
T
ABLE
4: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
BYTE
ALIGNMENT
................................................................................... 16
T
ABLE
5: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
DWORD
ALIGNMENT
............................................................................... 16
2.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 17
F
IGURE
6. T
HE
G
LOBAL
I
NTERRUPT
R
EGISTER
, INT0, INT1, INT2
AND
INT3.................................................................................. 18
T
ABLE
6: UART C
HANNEL
[7:0] I
NTERRUPT
S
OURCE
E
NCODING
..................................................................................................... 18
T
ABLE
7: UART C
HANNEL
[7:0] I
NTERRUPT
C
LEARING
: .................................................................................................................. 18
2.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
00-00).............................................................................................................................................................................. 19
F
IGURE
7. T
IMER
/C
OUNTER
CIRCUIT
............................................................................................................................................... 19
T
ABLE
8: TIMER CONTROL R
EGISTERS
...................................................................................................................................... 19
2.2.3 8XMODE [7:0] (DEFAULT 0X00)................................................................................................................................ 20
2.2.4 REGA [15:8] RESERVED ........................................................................................................................................... 20
2.2.5 RESET [23:16] (DEFAULT 0X00)............................................................................................................................... 20
2.2.6 SLEEP [31:24] (DEFAULT 0X00)............................................................................................................................... 21
2.2.7 DEVICE IDENTIFICATION AND REVISION............................................................................................................... 21
2.2.8 REGB REGISTER ....................................................................................................................................................... 22
2.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS.............................................................................................................. 22
2.2.10 MPIO REGISTER ...................................................................................................................................................... 22
F
IGURE
8. M
ULTIPURPOSE
INPUT
/
OUTPUT
INTERNAL
CIRCUIT
........................................................................................................... 23
3.0 CRYSTAL OSCILLATOR / BUFFER ...................................................................................................25
F
IGURE
9. T
YPICAL
OSCILLATOR
CONNECTIONS
............................................................................................................................... 25
F
IGURE
10. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
........................................................................................ 25
4.0 TRANSMIT AND RECEIVE DATA .......................................................................................................26
4.1 FIFO
DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS IN 32-BIT
FORMAT. ........................................................................................................................................................ 26
4.1.1 NORMAL RX FIFO
DATA UNLOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700....................................... 26
4.1.2 SPECIAL RX FIFO
DATA UNLOADING AT LOCATIONS 0X180, 0X380, 0X580, AND 0X780.............................. 27
4.1.3 TX FIFO
DATA LOADING AT LOCATIONS 0X100, 0X300, 0X500, 0X700, 0X900, 0XB00, 0XD00, 0XF00.......... 27
4.2 FIFO
DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN
8-BIT FORMAT. .............................................................................................................................................. 28
T
ABLE
9: T
RANSMIT
AND
R
ECEIVE
D
ATA
R
EGISTER
IN
B
YTE
FORMAT
, 16C550
COMPATIBLE
............................................................ 28
5.0 UART ....................................................................................................................................................29
5.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 29
F
IGURE
11. B
AUD
R
ATE
G
ENERATOR
............................................................................................................................................. 29
T
ABLE
10: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
........................................ 30
5.2 TRANSMITTER ............................................................................................................................................... 30
5.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 30
5.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................. 30
F
IGURE
12. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
............................................................................................................ 31