xr
5V PCI BUS OCTAL UART
XR17D158
REV. 1.2.1
II
5.2.3 TRANSMITTER OPERATION IN FIFO MODE........................................................................................................... 31
5.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 31
F
IGURE
13. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
................................................................................... 31
5.3 RECEIVER ...................................................................................................................................................... 32
5.3.1 RECEIVE HOLDING REGISTER (RHR).................................................................................................................... 32
5.3.2 RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................... 32
F
IGURE
14. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
.................................................................................................................. 32
5.3.3 RECEIVER OPERATION WITH FIFO......................................................................................................................... 33
F
IGURE
15. R
ECEIVER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
......................................................................................... 33
5.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .............................. 33
T
ABLE
11: A
UTO
RTS/CTS
OR
DTR/DSR F
LOW
C
ONTROL
S
ELECTION
.......................................................................................... 33
F
IGURE
16. A
UTO
RTS/DTR
AND
CTS/DSR F
LOW
C
ONTROL
O
PERATION
...................................................................................... 34
5.5 INFRARED MODE .......................................................................................................................................... 35
F
IGURE
17. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
.......................................................................... 35
5.6 INTERNAL LOOPBACK ................................................................................................................................. 36
F
IGURE
18. I
NTERNAL
L
OOP
B
ACK
................................................................................................................................................. 36
5.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING ....................................... 37
T
ABLE
12: UART CHANNEL CONFIGURATION REGISTERS ................................................................................................... 37
T
ABLE
13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4. ....... 38
5.8 REGISTERS .................................................................................................................................................... 39
5.8.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 39
5.8.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 39
5.8.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE................................................................ 39
5.8.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE.......................................................................................... 40
IER versus Receive FIFO Interrupt Mode Operation................................................................................................. 40
IER versus Receive/Transmit FIFO Polled Mode Operation..................................................................................... 40
5.8.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY............................................................................................ 41
T
ABLE
14: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
..................................................................................................................... 42
5.8.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY.................................................................................................. 42
T
ABLE
15: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
............................................................................................ 44
5.8.7 LINE CONTROL REGISTER (LCR) - READ/WRITE.................................................................................................. 45
T
ABLE
16: P
ARITY
SELECTION
........................................................................................................................................................ 46
5.8.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE ........................................................................................... 46
5.8.9 LINE STATUS REGISTER (LSR) - READ/ONLY....................................................................................................... 47
5.8.10 MODEM STATUS REGISTER (MSR) - READ-ONLY .............................................................................................. 48
5.8.11 MODEM STATUS REGISTER (MSR) - WRITE-ONLY............................................................................................. 49
T
ABLE
17: A
UTO
RS485 H
ALF
-
DUPLEX
D
IRECTION
C
ONTROL
D
ELAY
FROM
T
RANSMIT
-
TO
-R
ECEIVE
................................................. 49
5.8.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE................................................................................................. 50
5.8.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE.................................................................................... 50
T
ABLE
18: 16 S
ELECTABLE
H
YSTERESIS
L
EVELS
W
HEN
T
RIGGER
T
ABLE
-D
IS
S
ELECTED
................................................................ 51
5.8.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE..................................................................................... 51
T
ABLE
19: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
........................................................................................................................ 52
5.8.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ-ONLY ......................................................................... 53
5.8.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE-ONLY........................................................................ 53
5.8.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ-ONLY............................................................................ 53
5.8.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE-ONLY............................................................................ 53
T
ABLE
20: UART RESET CONDITIONS...................................................................................................................................... 54
6.0 PROGRAMMING EXAMPLES .............................................................................................................55
6.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS .................. 55
ABSOLUTE MAXIMUM RATINGS ..................................................................................56
ELECTRICAL CHARACTERISTICS................................................................................56
DC ELECTRICAL CHARACTERISTICS FOR 5V PCI B
US
I
NTERFACE
(VIO = 4.75-5.25V, VCC = 4.5-5.5V)
56
AC ELECTRICAL CHARACTERISTICS FOR 5V PCI B
US
I
NTERFACE
(VIO = 4.75-5.25V, VCC = 4.5 - 5.5V)
57
DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI B
US
I
NTERFACE
(VIO = 3.0-3.6V, VCC = 4.5 - 5.5V)
58
TA=0o to 70oC (-40o to +85oC for industrial grade package)................................................................................... 58
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI B
US
I
NTERFACE
(VIO = 3.0-3.6V, VCC = 4.5 - 5.5V)
59
TA=0o to 70oC (-40o to +85oC for industrial grade package)................................................................................... 59
F
IGURE
19. T
IMING
F
OR
E
XTERNAL
C
LOCK
I
NPUT
AT
XTAL1 P
IN
.................................................................................................... 60
F
IGURE
20. PCI B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
R
EAD
AND
W
RITE
OPERATION
................................................................. 61