XR17V254
10
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
NOTE: EWR=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-
Clear.
1.2
Power Management Registers
The Power Management Registers are implemented in 2 DWORDs starting at address offset 0x40 of the PCI
local bus configuration space. The bit definitions of these registers are shown in Table 2 below. The V254
complies with Revision 1.1 of the PCI Power Management Interface Specification.
0x24
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x28
31:0
RO
Reserved
0x00000000
0x2C
31:16
EWR
Subsystem ID (write from external EEPROM by customer)
0x0000
15:0
EWR
Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
0x0000
0x30
31:0
RO
Expansion ROM Base Address (Unimplemented)
0x00000000
0x34
31:8
RO
Reserved (returns zeros)
0x000000
7:0
RO
Capability Pointer (Implemented for Power Management)
0x40
0x38
31:0
RO
Reserved (returns zeros)
0x00000000
0x3C
31:24
RO
Unimplemented MAXLAT
0x00
23:16
RO
Unimplemented MINGNT
0x00
15:8
RO
Interrupt Pin, use INTA#.
0x01
7:0
RWR
Interrupt Line.
0xXX
TABLE 2: POWER MANAGEMENT REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
0x40
31:16
See Below
Power Management Capabilities (PMC)
See Below
31:27
RO
PME Support (PME# can be asserted from D3hot only)
01000b
26:20
RO
Reserved or Not Supported
0000000b
19
RO
PME Clock (PCI clock is required for PME# generation)
1b
18:16
RO
Version
010b
15:8
RO
Next Item Pointer
0x00
7:0
RO
Capability ID
0x01
0x44
31:24
RO
Unimplemented Data Register
0x00
23:16
RO
Unimplemented Bridge Support Extensions
0x00
15:0
See Below
Power Management Control/Status Register (PMCSR)
See Below
15
RWC
PME_Status
0b
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)