參數(shù)資料
型號: XR17V354IB-E4-EVB
廠商: Exar Corporation
文件頁數(shù): 24/66頁
文件大小: 0K
描述: EVAL BRD FOR XR17V354-E4 176BGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR17V354
已供物品:
其它名稱: 1016-1612
XR17V354IB-E4-EVB-ND
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 3 Receive Data in 32-bit alignment through the Configuration Register Address
0x0100, 0x0500, 0x0900 and 0x0D00
XR17V354
30
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
2.1.2
Special Rx FIFO Data Unloading at locations 0x0200, 0x0600, 0x0A00 and 0x0E00
The XR17V354 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x0200 (channel 0), 0x0600 (channel 1), 0x0A00 (channel 2) and 0x0E00 (channel 3).
The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following tables
show this clearly.
READ RX FIFO,
WITH LSR
ERRORS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
PCI Bus
Data Bit-0
Channel 0 to 3 Receive Data with Line Status Register in 32-bit alignment through the Configuration
Register Address 0x0200, 0x0600, 0x0A00 and 0x0E00
2.1.3
Tx FIFO Data Loading at locations 0x100, 0x500, 0x900 and 0xD00
The TX FIFO data can be loaded 32 bits (4 bytes) at a time at memory locations 0x0100 (channel 0), 0x0500
(channel 1), 0x0900 (channel 2) and 0x0D00 (channel 3).
WRITE TX FIFO
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
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