REV. 1.0.3 MSR[3]: Delta CD# Input Flag Logic 0 = N" />
參數(shù)資料
型號(hào): XR17V354IB-E4-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 52/66頁(yè)
文件大小: 0K
描述: EVAL BRD FOR XR17V354-E4 176BGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR17V354
已供物品:
其它名稱: 1016-1612
XR17V354IB-E4-EVB-ND
XR17V354
56
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit [3]).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a LOW to a HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit [3]).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit [3]).
4.11
Modem Status Register (MSR) - Write Only
The upper four bits [7:4] of this register set the delay in number of bits time for the auto RS-485 turn around
from transmit to receive.
MSR [7:4]: Auto RS485 Turn-Around Delay (requires EFR bit [4]=1)
When Auto RS485 feature is enabled (FCTR bit [5]=1) and RTS#/DTR# output is connected to the enable input
of a RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the
last transmitted character. This delay controls when to change the state of RTS#/DTR# output. This delay is
very useful in long-cable networks. Table 18 shows the selection. The bits are enabled by EFR bit-4.
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