參數(shù)資料
型號: XR17V354IB-E4-EVB
廠商: Exar Corporation
文件頁數(shù): 25/66頁
文件大小: 0K
描述: EVAL BRD FOR XR17V354-E4 176BGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標準包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR17V354
已供物品:
其它名稱: 1016-1612
XR17V354IB-E4-EVB-ND
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Transmit Data Byte n+3
Transmit Data Byte n+2
Transmit Data Byte n+1
Transmit Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 3 Transmit Data in 32-bit alignment through the Configuration Register Address
0x0100, 0x0500, 0x0900 and 0x0D00
XR17V354
31
REV. 1.0.3
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
2.2
FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 to channel 3 is shown in Table 10 below. The THR and RHR
for each channel 0 to 3 are located sequentially at address 0x0000, 0x0200, 0x0400 and 0x0600. Transmit
data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR
register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so
each bus operation can only write or read in bytes.
TABLE 10: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible)
CH0 0x0000 Read THR
CH0 0x0000 Write RHR
CH1 0x4000 Read THR
CH1 0x4000 Write RHR
CH2 0x8000 Read THR
CH3 0xC000 Read THR
CH2 0x8000 Write RHR
CH3 0xC000 Write RHR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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