TABLE 18: AUTO RS485 H
參數(shù)資料
型號: XR17V354IB-E8-EVB
廠商: Exar Corporation
文件頁數(shù): 53/66頁
文件大?。?/td> 0K
描述: EVAL BRD FOR XR17V354-E8 176BGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR17V354
已供物品:
其它名稱: 1016-1613
XR17V354IB-E8-EVB-ND
TABLE 18: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
DELAY IN DATA BIT(S) TIME
0
1
0
1
0
2
0
1
3
0
1
0
4
9
1
0
1
5
0
1
0
6
0
1
7
1
0
8
1
0
1
9
1
0
1
0
10
1
0
1
11
1
0
12
1
0
1
13
1
0
14
1
15
XR17V354
57
REV. 1.0.3
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
MSR [3]: Transmitter Disable
This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set
to a logic 1, the bytes already in the FIFO will not be sent out. Also, any more data loaded into the FIFO will
stay in the FIFO and will not be sent out. When this bit is set to a logic 0, the bytes currently in the TX FIFO will
be sent out. Please note that setting this bit to a logic 1 stops any character from going out. Also, this bit must
be a logic 0 for the Send Char Immediate function (see MCR[3]).
Logic 0 = Enable Transmitter (default).
Logic 1 = Disable Transmitter.
MSR[7]
MSR[6]
MSR[5]
MSR[4]
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