REV. 1.0.3 FUNCTIONAL DESCRIPTION The XR17V354 (V354) integrates the functions of four indepe" />
參數(shù)資料
型號: XR17V354IB-E8-EVB
廠商: Exar Corporation
文件頁數(shù): 65/66頁
文件大?。?/td> 0K
描述: EVAL BRD FOR XR17V354-E8 176BGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR17V354
已供物品:
其它名稱: 1016-1613
XR17V354IB-E8-EVB-ND
XR17V354
8
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
FUNCTIONAL DESCRIPTION
The XR17V354 (V354) integrates the functions of four independent enhanced 16550 UARTs, a general
purpose 16-bit timer/counter, and 16 multi-purpose I/Os (MPIOs). Each UART channel has its own 16550
UART compatible configuration register set for individual channel control, status and data transfer. The device
configuration registers include a set of four consecutive interrupt source registers that provides interrupt status
for all four UARTs, timer/counter, MPIOs and a sleep wake-up indicator. Additionally, each UART channel has
256-byte of transmit and receive FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control, automatic
XON/XOFF, special character flow control, programmable transmit and receive FIFO trigger levels, infrared
encoder/decoder (IrDA ver. 1.1), and a programmable fractional baud rate generator with a prescaler of divide
by 1 or 4, and a data rate up to 25 Mbps with the 4X sampling rate.
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
A set of local bus configuration space register is provided. These registers provide the PCI vendor ID, device
ID, sub-vendor ID, product model number, resources and capabilities which is collected by the host during the
auto configuration phase that follows immediately after a power up or system reset/reboot. After the host has
sorted out all devices on the bus, it defines and download the operating conditions to the cards. One of the
definitions is the base address loaded into the Base Address Register (BAR) where the card will be operating
in the PCI local bus memory space. All this is described in more detail in “Section 1.1, PCI LOCAL BUS
EEPROM INTERFACE
An external 93C46 EEPROM is used to store words of information such as PCI Vendor ID, PCI Device ID,
Class Code, etc. Details of this information can be found in “Section 1.2, EEPROM Interface” on page 13.
This information is only used with the plug-and-play auto configuration of the PCI local bus. These data provide
automatic hardware installation onto the PCI bus. The EEPROM interface consists of 4 signals, EEDI, EEDO,
EECS, and EECK. The EEPROM is not needed when auto configuration is not required in the application.
However, if your design requires non-volatile memory for other purpose, it is possible to store and retrieve data
on the EEPROM through a special PCI device configuration register. See application note DAN112 for its
programming details.
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