REV. 1.0.4 NOTE: MCR bits" />
參數(shù)資料
型號(hào)： XR17V358IB-E4-EVB
廠商： Exar Corporation
文件頁數(shù)： 39/68頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E4
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱： 1016-1295
XR17V358
44
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
NOTE: MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V358. They are present for 16C550
compatibility during Internal loopback, see
3.6
Transmitter
The transmitter section comprises of a 256 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit [0]. TSR shifts out every data bit with the 16X or 8X
internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of
data bits, inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are
reported in the Line Status Register (LSR bit [6:5]).
3.6.1
Transmit Holding Register (THR)
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (bit [0]) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 256 bytes when FIFO operation is enabled by FCR bit[0]. A THR empty
interrupt can be generated when it is enabled in IER bit [1].
3.6.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit [5]) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit [1]) when it is
enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
1 0 0 1
EFR
R/W
Auto
CTS/
DSR
Enable
Auto
RTS/
DTR
Enable
Special
Char
Select
Enable
IER [7:5],
ISR [5:4],
FCR[5:4],
MCR[7:5],
MSR
Soft-
ware
Flow
Cntl
Bit [3]
Soft-
ware
Flow
Cntl
Bit [2]
Soft-
ware
Flow
Cntl
Bit [1]
Software
Flow Cntl
Bit [0]
1 0 1 0
TXCNT
R
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
1 0 1 0
TXTRG
W
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
1 0 1 1
RXCNT
R
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
1 0 1 1
RXTRG
W
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
1 1 0 0
XCHAR
R
0
TX Xon
Indicator
TX Xoff
Indicator
Xon Det.
Indicator
Xoff Det.
Indicator
Self clear
after read
1 1 0 0
XOFF1
W
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit-2
Bit [1]
Bit [0]
1 1 0 1
XOFF2
W
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit-2
Bit [1]
Bit [0]
1 1 1 0
XON1
W
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit-2
Bit [1]
Bit [0]
1 1 1 1
XON2
W
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit-2
Bit [1]
Bit [0]
TABLE 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
READ/
WRITE
BIT [7]
BIT [6]
BIT [5]
BIT [4]
BIT [3]
BIT [2]
BIT[1]
BIT [0]
COMMENT
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