REV. 1.0.4 HIGH PERFORMANCE OCTAL PCI EXPRESS UART 4.7 Line Control Register (LCR) - Read/Write The Line Control Regi" />
參數(shù)資料
型號(hào)： XR17V358IB-E8-EVB
廠(chǎng)商： Exar Corporation
文件頁(yè)數(shù)： 49/68頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E8
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱(chēng)： 1016-1296
XR17V358
53
REV. 1.0.4
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
4.7
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM, DLD) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers (DLL, DLM and DLD) are selected.
LCR[6]: Transmit Break Enable
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW, state). This condition remains until disabled by setting LCR bit [6] to a logic 0.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR bit [5] selects the forced parity format.
LCR bit [5] = logic 0, parity is not forced (default).
LCR bit [5] = logic 1 and LCR bit [4] = logic 0, parity bit is forced to a logical 1for the transmit and receive
data.
LCR bit [5] = logic 1 and LCR bit [4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Table-C
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
16C654
Table-D
1
X
Programmable
via RXTRG
register
Programmable
via TXTRG
register
16L2752, 16L2750,
16C2852, 16C850,
16C854, 16C864
TABLE 16: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER
TABLE
FCTR
BIT [7]
FCTR
BIT [6]
FCR
BIT [7]
FCR
BIT [6]
FCR
BIT [5]
FCR
BIT [4]
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
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