REV. 1.1.0 I2C/SPI UART WITH 64-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’ and requires at le" />
參數資料
型號： XR20M1170IG16-F
廠商： Exar Corporation
文件頁數： 22/56頁
文件大?。?/td> 0K
描述： IC UART FIFO I2C/SPI 64B 16TSSOP
產品培訓模塊： UART Product Overview
產品變化通告： Packaging Change 14/Jul/2010
標準包裝： 95
特點： *
通道數： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 2.25 V ~ 3.6 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 管件
其它名稱： 1016-1297-5
XR20M1170
29
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’ and requires at least 3 XTAL clocks to reset.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’ and requires at least 3 XTAL clocks to reset.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: Reserved
This is a legacy register bit that does not have any functionality in the XR20M1170.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of spaces in the FIFO is above the selected trigger level, or when it gets empty in case that the FIFO
did not get filled over the trigger level on last re-load. Table 10 shows the selections. The UART will issue a
transmit interrupt when the number of available spaces in the FIFO is less than the transmit trigger level.
Table 10 shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO is greater than the receive trigger level or when a receive data
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
BIT-7
BIT-6
BIT-5
BIT
-4
RECEIVE
TRIGGER LEVEL
(CHARACTERS)
TRANSMIT
TRIGGER LEVEL
(SPACES)
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
FCR
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參數描述
XR20M1170IG16-F 制造商:Exar Corporation 功能描述:IC SGL UART 16MBPS 3.63V 16-TSSOP 制造商:Exar Corporation 功能描述:IC, SGL UART, 16MBPS, 3.63V, 16-TSSOP
XR20M1170IG16TR-F 制造商:Exar Corporation 功能描述:UART 1-CH 64Byte FIFO 1.8V/2.5V/3.3V 16-Pin TSSOP T/R 制造商:Exar Corporation 功能描述:XR20M1170IG16TR-F 制造商:EXAR 功能描述:UART 1-CH 64Byte FIFO 1.8V/2.5V/3.3V 16-Pin TSSOP T/R
XR20M1170IG24 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR20M1170IG24-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR20M1170IG24TR-F 制造商:Exar Corporation 功能描述:UART 1-CH 64Byte FIFO 1.8V/2.5V/3.3V 24-Pin TSSOP T/R 制造商:Exar Corporation 功能描述:XR20M1170IG24TR-F
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