REV. 1.1.0 I2C/SPI UART WITH 64-BYTE FIFO the stop bit of the character in process is shifted out. Transmission is resumed after t" />
參數(shù)資料
型號： XR20M1170IG16-F
廠商： Exar Corporation
文件頁數(shù)： 9/56頁
文件大?。?/td> 0K
描述： IC UART FIFO I2C/SPI 64B 16TSSOP
產(chǎn)品培訓模塊： UART Product Overview
產(chǎn)品變化通告： Packaging Change 14/Jul/2010
標準包裝： 95
特點： *
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 2.25 V ~ 3.6 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 管件
其它名稱： 1016-1297-5
XR20M1170
17
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
FIGURE 17. AUTO RTS AND CTS FLOW CONTROL OPERATION
RTSA#
CTSB#
RXA
TXB
Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON
OFF
ON
Suspend
Restart
RTS High
Threshold
Data Starts
ON
OFF
ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data
RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#
CTSA#
RXB
TXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
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XR20M1170IG16-F 制造商:Exar Corporation 功能描述:IC SGL UART 16MBPS 3.63V 16-TSSOP 制造商:Exar Corporation 功能描述:IC, SGL UART, 16MBPS, 3.63V, 16-TSSOP
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XR20M1170IG24 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR20M1170IG24-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR20M1170IG24TR-F 制造商:Exar Corporation 功能描述:UART 1-CH 64Byte FIFO 1.8V/2.5V/3.3V 24-Pin TSSOP T/R 制造商:Exar Corporation 功能描述:XR20M1170IG24TR-F
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