參數(shù)資料
型號: XR20M1172IL32-F
廠商: Exar Corporation
文件頁數(shù): 20/55頁
文件大小: 0K
描述: IC UART FIFO I2C/SPI 64B 32QFN
標(biāo)準(zhǔn)包裝: 490
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
其它名稱: 1016-1477
XR20M1172IL32-F-ND
XR20M1172
27
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 17.
4.2
Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 15.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
0x0B
IOState
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x0C
IOIntEna RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x0D
reserved
-
0
0x0E IOControl RD/WR
0
UART
SW
Reset
GPIO or
Modem
IO Ch B
GPIO or
Modem
IO Ch A
IOLatch
0x0F
EFCR
RD/WR
Fast IR
Mode
0
Auto
RS485
Invert
Auto
RS485
Enable
0
TX
Disable
RX
Disable
9-Bit
Mode
Baud Rate Generator Divisor
0x00
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
LCR
≠0xBF
0x01
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x02
DLD
RD/WR
Bit-7
Bit-6
4X Mode 8X Mode
Frac-
tional
Divisor
Bit-3
Frac-
tional
Divisor
Bit-2
Frac-
tional
Divisor
Bit-1
Frac-
tional
Divisor
Bit-0
LCR[7]=1
LCR
≠0xBF
EFR[4]=1
Enhanced Registers
0x02
EFR
RD/WR
Auto
CTS
Enable
Auto RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
DLD
Soft-
ware
Flow
Cntl
Bit-3
Software
Flow Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
0x04
XON1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x05
XON2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x06
XOFF1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x07
XOFF2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
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