REV. 1.3.0 2-CH FULL-SPEED USB UART 3.3.5 CHARACTER_FORMAT Register Description (Read/Write) This register controls the character " />
參數(shù)資料
型號(hào): XR21V1412IL32-F
廠商: Exar Corporation
文件頁(yè)數(shù): 14/32頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO USB DUAL 32QFN
產(chǎn)品培訓(xùn)模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
特色產(chǎn)品: XR21V141x Full-Speed USB UART
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 托盤(pán)
配用: 1016-1301-ND - EVAL BOARD FOR XR21V1412IL
其它名稱: 1016-1302
XR21V1412
21
REV. 1.3.0
2-CH FULL-SPEED USB UART
3.3.5
CHARACTER_FORMAT Register Description (Read/Write)
This register controls the character format such as the word length (7, 8 or 9), parity (odd, even, forced ’0’, or
forced ’1’) and number of stop bits (1 or 2).
CHARACTER_FORMAT[3:0]: Data Bits.
All other values for CHARACTER_FORMAT[3:0] are reserved.
CHARACTER_FORMAT[6:4]: Parity Mode Select
These bits select the parity mode. If 9-bit data mode has been selected, then writing to these bits will not have
any effect. In other words, there will not be an additional parity bit.
CHARACTER_FORMAT[7]: Stop Bit select
This register selects the number of stop bits to add to the transmitted character and how many stop bits to
check for in the received character.
3.3.6
FLOW_CONTROL Register Description (Read/Write)
These registers select the flow control mode. These registers should only be written to when the UART is
disabled.
Writing to the FLOW_CONTROL register when the UART is enabled will result in undefined
behavior. Note that the FLOW_CONTROL register settings are used in conjunction with the GPIO_MODE
register.
TABLE 10: DATA BITS
DATA BITS
CHARACTER_FORMAT[3:0]
7
0111
8
1000
9
1001
TABLE 11: PARITY SELECTION
BIT-6
BIT-5
BIT-4
PARITY SELECTION
0
No parity
0
1
Odd parity
0
1
0
Even parity
0
1
Force parity to mark, “1”
1
0
Force parity to space, “0”
TABLE 12: STOP BIT SELECTION
BIT-7
NUMBER OF STOP BITS
0
1 stop bit
2
2 stop bits
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