FIGURE 21. TRANSMIT R
參數(shù)資料
型號： XR68M752IM-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 41/54頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR68M752 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit
D0:D7
Stop
Bit
D0:D7
T
WT
TXNonFIFO
T
WT
T
WT
T
WRI
T
WRI
T
WRI
T
SRT
T
SRT
T
SRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read
(Loading data
into THR)
IER[1]
enabled
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
S
T
SSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
XR16M752/XR68M752
46
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
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