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參數(shù)資料
型號(hào)： XR88C681CJTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 26/101頁(yè)
文件大小： 0K
描述： IC UART CMOS DUAL 44PLCC
標(biāo)準(zhǔn)包裝： 500
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
其它名稱： XR88C681CJTR-F-ND
XR88C681
30
Rev. 2.11
INT
INTE
D0
D1
D2
D3
D4
D5
D6
D7
8080A CPU
8228
Bi-Directional
BUS Driver
XR88C681
DUART
-INTR
INTA
Vcc
DBIN
U1
U2
U3
U4
U5
U6
Figure 7. Circuit Schematic depicting approach to Interface the XR88C681 DUART
to the 8080A CPU, for “External” Vectored Interrupt Processing
(Interrupt Service Routine resides at 002016 in Memory)
Vcc
SN74LS244
-OE1 -OE2
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
Since the 8080A CPU can support up to 8 different RST
instructions, it can support up to 8 different
interrupt-driven peripheral devices. This can be achieved
by replicating the approach, presented in
Figure 7, and
by hardwiring the op-codes for each of the RESTART
instructions to the inputs of the Data Buffers (see
Table 10).
These Data Buffers should be enabled only during the
-INTA cycle, and only when their associated peripheral
requested the interrupt service.
C.6.1.3 8085 Microprocessor
The 8085 CPU is another early Intel microprocessor,
although it is more advanced than the 8080A CPU. Some
of the advancements that were made in the transition
from the 8080A to the 8085 include combining the Clock
Generator functions of the 8224 onto the CPU chip,
adding a non-maskable interrupt request, adding 3
“direct” interrupt request input pins, and adding some
form of interrupt priority. The 8085 still requires some glue
logic in order to produce the Control Bus signals (i.e.,
-IOR, -IOW, -MEMR, -MEMW). Further, in order to
minimize pin count, the 8085 contains a multiplexed
Address/Data Bus (AD0 - AD7). Specifically, the lower 8
bits of the Address Bus share pins with the 8 bit Data Bus.
Hence, a 74LS373 8-bit latch is needed in order to
demultiplex the Address and Data buses.
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