Figure 44 shows two DUART devices, one labeled “Transmitting Device” and the other, “Receiving Device”. This example star" />
參數(shù)資料
型號: XR88C681CJTR-F
廠商: Exar Corporation
文件頁數(shù): 84/101頁
文件大小: 0K
描述: IC UART CMOS DUAL 44PLCC
標(biāo)準(zhǔn)包裝: 500
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
其它名稱: XR88C681CJTR-F-ND
XR88C681
83
Rev. 2.11
Figure 44 shows two DUART devices, one labeled
“Transmitting Device” and the other, “Receiving Device”.
This example starts with the assumption that the
“Transmitter Device” has been programmed such that
MR2A[5] = 1, which results in programming the
“Transmitting Device” for Transmitter-RTS Control. This
example further assumes that the “Transmitting Device”
has been programmed such that MR2A[4] = 1. According
to
Section G.3, the Transmitter of Channel A of the
“Transmitting Device” has now been programmed to be
under -CTSA input control.
In the case of the “Receiving Device”, IP2 (RTS-in) has
been programmed to generate an “Input Port Change of
State” interrupt request to the CPU. The firmware for the
Interrupt Service Routines is written such that if the IP2
input were to change and IPCR[2] = 0, the CPU would
“write” [D7,..., D0] = [0, 0, 0, 0, 1, 0, 0, 0] to DUART
address 0E16. In this step, the Interrupt Service Routine
would invoke the “SET OUTPUT PORT BITS
COMMAND”, and in the process toggle OPR[3] to a logic
“high” and the Output Port pin, OP3, (CTS-out) to a logic
“l(fā)ow”. This would, in turn, assert the -CTSA input of the
“Transmitting Device” and allow it to transmit data to the
“Receiving Device”.
Once Channel A Transmitter has emptied both its THR
and TSR of data, it will negate the -RTSA output, via the
“Transmitter-RTS Control” feature. When the -RTSA
output the “Transmitting Device” is toggled “high”, the IP2
(RTS-in) is also toggled “high”, thereby generating
another “Input Change of State” interrupt request to the
CPU. With IPCR[2] = 1, the likely Interrupt Service
Routine would be to “Write” [D7,..., D0] = [0, 0, 0, 0, 1, 0, 0,
0] to DUART address 0F16. In this step, the Interrupt
Service Routine would invoke the “CLEAR OUTPUT
PORT BITS COMMAND”, and in the process toggle OP3
(CTS-out) “high”. This would in turn negate the -CTSA
input of the “Transmitting Device” and inhibit the
transmission of data from the Channel A of the
“Transmitting Device”.
Figure 45 presents a Flow Diagram which depicts an
Algorithm that could be used to implement the
Transmitter-Control RTS/CTS Handshaking Mode.
Please note that the shaded block pertain to occurrences
within the “Receiving Device”. Whereas the “White” block
pertain to operation within the “Transmitting Device.”
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