Rev. 2.00 XRD98L61 PIXEL RATE CLOCKS SBLK, SPIX & ADCLK Sampling of the pixel Black Level is controlled by the SBLK pulse. When SBLK is " />
參數(shù)資料
型號: XRD98L61ZEVAL
廠商: Exar Corporation
文件頁數(shù): 18/38頁
文件大小: 0K
描述: EVAL BOARD FOR XRD98L61AIV
標準包裝: 1
系列: *
25
Rev. 2.00
XRD98L61
PIXEL RATE CLOCKS
SBLK, SPIX & ADCLK
Sampling of the pixel Black Level is controlled by the
SBLK pulse. When SBLK is low, the internal sample
Black switches in the CDS are ON, sampling the pixel
black level on the internal capacitors.
The AFE starts tracking the pixel Video Level, an
internal delay, after the rising edge of SBLK. The
internal delay is programmed by DelayB[8:6]. The
Figure 13. Detailed Pixel Rate Clock Timing for Default Register Settings
AFE holds the pixel Video Level on the rising edge of
SPIX.
The ADC will track the PGA output when ADCLK is
high. The ADC will hold the PGA output and start a
conversion when ADCLK goes low. The falling edge of
ADCLK should happen coincident with, or just before,
the rising edge of SBLK. ADCLK should be as close as
possible to 50% duty cycle.
Note:
The timing descriptions in this section are correct for the default conditions:
All Polarity bits = 0,
RSTreject = 0 (switch always ON),
SPIXopt = 0
SBLK
SPIX
CCD
Signal
t
PIX
ADCLK
t
BK
t
VD
t
DL
t
PW1
t
PW2
Black Sample Point
Video Sample Point
DB[11:0]
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