參數(shù)資料
型號: XRK32309CD-1
廠商: EXAR CORP
元件分類: 時鐘及定時
英文描述: LOW-COST 3.3V ZERO DELAY BUFFER
中文描述: 32309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 3/13頁
文件大?。?/td> 101K
代理商: XRK32309CD-1
PRELIMINARY
XRK32309
3
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
N
OTES
:
1.
2.
3.
4.
Weak pull-down.
Weak pull-down on all outputs.
Weak pull-ups on these inputs.
This output has an internal feedback for the PLL. The load on this output can be adjusted to change the skew
between the reference and output.
ZERO DELAY AND SKEW CONTROL
In order to achieve Zero Delay between the input reference and the output, all outputs, including FB, must be
equally loaded even when the FB output is not being used.
Being internally connected as the PLL feedback, the FB output's capacitive loading relative to the other
outputs can adjust the input to output delay according to the characteristic shown in Figure 3. This figure
provides a tool for mapping the required delay to the capacitive load difference required between the FB and
the Clock output of interest.
For zero output to output skew, the outputs have to be loaded equally as well.
T
ABLE
2: S
ELECT
I
NPUT
D
ECODING
S2
S1
QA0-QA3
QB0-QB3
FB
[4]
O
UTPUT
S
OURCE
0
0
Tri-Stated
Tri-Stated
Driven
PLL
0
1
Driven
Tri-Stated
Driven
PLL
1
0
Driven
Driven
Driven
Reference
1
1
Driven
Driven
Driven
PLL
F
IGURE
3. REF. I
NPUT
TO
QA
X
/QB
X
D
ELAY
VS
. L
OADING
D
IFFERENCE
BETWEEN
FB
AND
QA
X
/QB
X
P
INS
0
-30
500
1000
1500
-500
-1000
-1500
R
Output Load Difference: FB Load - QAx/QBx Load (pF)
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
Note: Target only, actual characterization curve may be slightly different.
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