參數(shù)資料
型號(hào): XRK32309CD-1
廠商: EXAR CORP
元件分類: 時(shí)鐘及定時(shí)
英文描述: LOW-COST 3.3V ZERO DELAY BUFFER
中文描述: 32309 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 5/13頁
文件大?。?/td> 101K
代理商: XRK32309CD-1
PRELIMINARY
XRK32309
5
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
N
OTES
:
5.
REF input has a threshold voltage of V
DD
/2.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
All parameters specified with loaded outputs.
6.
7.
T
ABLE
6: S
WITCHING
C
HARACTERISTICS
FOR
XRK32309SC-1 C
OMMERCIAL
T
EMPERATURE
D
EVICES[7]
P
ARAMETER
N
AME
T
EST
C
ONDITIONS
M
IN
T
YP
M
AX
U
NIT
t
1
Output Frequency
30-pF load
10-pF load
10
10
-
100
120
MHz
MHz
DC
Duty Cycle
[6]
= t
2
÷
t
1
Measured at 1.4V, F
OUT
=66.67MHz
40.0
50.0
60.0
%
t
3
Rise Time
[6]
Measured between 0.8V and 2.0V
-
-
2.50
ns
t
4
Fall Time
[6]
Measured between 0.8V and 2.0V
-
-
2.50
ns
t
5
Output to Output Skew
[6]
All outputs equally loaded
-
-
250
ps
t
6A
Delay, REF Rising Edge to
FB Rising Edge
[6]
Measured at V
DD
/2
-
0
±
350
ps
t
6B
Delay, REF Rising Edge to
FB Rising Edge
[6]
Measured at V
DD
/2. Measured in PLL
Bypass Mode
1
5
8.7
ns
t
7
Device to Device Skew
[6]
Measured at V
DD
/2 on the FB pins of
devices
-
0
700
ps
t
J
Cycle to Cycle Jitter
[6]
Measured at 66.67MHz, loaded outputs
-
-
200
ps
t
LOCK
PLL Lock Time
[6]
Stable power suppy, valid clock
presented on REF pin
-
-
1.0
ms
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