參數(shù)資料
型號: XRK69773IR
廠商: EXAR CORP
元件分類: XO, clock
英文描述: 1:12 LVCMOS PLL CLOCK GENERATOR
中文描述: 240 MHz, OTHER CLOCK GENERATOR, PQFP52
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52
文件頁數(shù): 8/12頁
文件大?。?/td> 98K
代理商: XRK69773IR
XRK69773
PRELIMINARY
8
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
3.0
QSYNC TIMING
XRK69773 INDIVIDUAL OUTPUT DISABLE (STOP CLOCK) CIRCUITRY
The user can write to the serial input register through the STOP_DATA input by supplying a logic ’0’ start bit
followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the
free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the XRK69773 can
sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. A logic "0" to any
stop bit location will disable the corresponding device output while a logic "1" will enable. All outputs are by
default, enabled.
F
IGURE
4. QSYNC T
IMING
D
IAGRAM
F
IGURE
5. S
TOP
C
LOCK
C
IRCUIT
P
ROGRAMMING
f
VCO
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
QA
QC
QSYNC
1:1 Mode
2:1 Mode
QA
QC
QSYNC
QA(/4)
QSYNC
3:1 Mode
3:2 Mode
QC(/6)
QC(/2)
QSYNC
QA(/6)
2
8
2
9
3
0
3
1
QA(/6)
QSYNC
QC(/8)
QC(/2)
QSYNC
QA(/8)
4:1 Mode
4:3 Mode
QA(/12)
QSYNC
QC(/2)
6:1 Mode
START
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
STOP_CLK
STOP_DATA
相關PDF資料
PDF描述
XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR
XRK69774CR 1:14 LVCMOS PLL CLOCK GENERATOR
XRK69774IR 1:14 LVCMOS PLL CLOCK GENERATOR
XRK697H73 1:12 LVCMOS PLL CLOCK GENERATOR
XRK697H73CR 1:12 LVCMOS PLL CLOCK GENERATOR
相關代理商/技術參數(shù)
參數(shù)描述
XRK69774 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR
XRK69774CR 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR
XRK69774IR 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR
XRK697H73 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR
XRK697H73CR 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR