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參數(shù)資料
| 型號： | XRK69773IR |
| 廠商： | EXAR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 1:12 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 240 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | XRK69773IR |
PRELIMINARY
XRK69773
9
REV. P1.0.0
1:12 LVCMOS PLL CLOCK GENERATOR
F
IGURE
6. O
UTPUT
-
TO
-
OUTPUT
S
KEW
t
SK(O)
F
IGURE
7. P
ROPOGATION
DELAY
(t
()
,
STATIC
PHASE
OFFSET
)
TEST
REFERENCE
F
IGURE
8. O
UTPUT
D
UTY
C
YCLE
(DC)
F
IGURE
9. I/O J
ITTER
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device.
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
t
SK(O)
FB_IN
t
()
CCLKx
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
tp
T
0
DC=t
P
/T
0
x 100%
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
V
CC
V
CC
÷2
GND
FB_IN
CCLKx
T
JIT(I/O)
= |T
0
-T
1
mean |
The deviation in t
0
for a controlled edge with respect to a t
0
mean in a random
sample of cycles
相關PDF資料 |
PDF描述 |
|---|---|
| XRK69774 | 1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774CR | 1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774IR | 1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73 | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73CR | 1:12 LVCMOS PLL CLOCK GENERATOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRK69774 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
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