Rev. 2.0.0 internally generated jitter is a function of the PLL bandwidth, which in turn is a function of the input 1s density. For" />
參數(shù)資料
型號: XRT7295AEIWTR
廠商: Exar Corporation
文件頁數(shù): 13/15頁
文件大?。?/td> 0K
描述: IC E3 LINE RECEIVER 20SOJ
標(biāo)準(zhǔn)包裝: 1,000
類型: 接收器
驅(qū)動器/接收器數(shù): 0/1
規(guī)程: E3
電源電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 20-BSOJ
供應(yīng)商設(shè)備封裝: 20-SOJ
包裝: 帶卷 (TR)
XRT7295AE
7
Rev. 2.0.0
internally generated jitter is a function of the PLL
bandwidth, which in turn is a function of the input 1s
density. For higher 1s densities, the amount of gener-
ated jitter decreases. Generated jitter also depends on
the quality of the power supply bypassing networks
used. Figure 8 shows the suggested bypassing net-
work, and Table 3 lists the typical generated jitter
performance achievable with this network.
Figure 4. Pulse Mask at the 34.368 Mbit/s Interface
Parameter
Value
Pulse Shape (Nominally Rectangular)
All marks of a valid signal must conform with the mask
(see Figure 4), irrespective of the sign
Pair(s) in Each Direction
One coaxial pair
Test Load Impedance
75
Resistive
Nominal Peak Voltage of a Mark (Pulse)
1.0V
Peak Voltage of a Space (No Pulse)
0V +/-0.1V
Nominal Pulse Width
14.55ns
Ratio of the Amplitudes of Positive and Negative Pulses
0.95 to 1.05
at the Center of a Pulse Interval
Ratio of the Widths of Positive and Negative Pulses
0.95 to 1.05
at the Nominal Half Amplitude
Table 2. E3 Pulse Specification at the Transmitter Output Port
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