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參數(shù)資料
| 型號： | XRT7295AEIWTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC E3 LINE RECEIVER 20SOJ |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/1 |
| 規(guī)程： | E3 |
| 電源電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-BSOJ |
| 供應(yīng)商設(shè)備封裝： | 20-SOJ |
| 包裝： | 帶卷 (TR) |
XRT7295AE
3
Rev. 2.0.0
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
GNDA
Analog Ground.
2
R
IN
I
Receive Input. Unbalanced analog receive input
3,6
TMC1-TMC2
I
Test Mode Control 1 and 2. Internal test modes are enabled within the device
by using TMC1 and TMC2. Users must tie these pins to the ground plane.
4,5
LPF-1-LPF-2
I
PLL Filter 1 and 2. An external capacitor (0.1
F +/-20%) is connected
between these pins (See Figure 3).
7
RLOS
O
Receive Loss-of-Signal. This pin is set high on loss of signal at the receive
input.
8
RLOL
O
Receive PLL Loss-of-Lock. This pin is set high on loss of PLL frequency lock.
9
GNDD
Digital Ground for PLL Lock. Ground lead for all circuitry running
synchronously with PLL clock.
10
GNDC
Digital Ground for EXCLK. Ground lead for all circuitry running
synchronously with EXCLK.
11
V
DDD
5V Digital Supply (+/-10%) for PLL Clock. Power for all circuitry running
synchronously with PLL clock.
12
V
DDC
5V Digital Supply (+/-10%) for EXCLK. Power for all circuitry running
synchronously with EXCLK.
13
EXCLK
I
External Reference Clock. A valid E3 (34.368MHz +/-100ppm) clock must be
provided at this input. The duty cycle of EXCLK, referenced to V
DD/2 levels,
must be 40%-60%.
14
RCLK
O
Receive Clock. Recovered clock signal to the terminal equipment.
15
RNDATA
O
Receive Negative Data. Negative pulse data output to the terminal
equipment.
16
RPDATA
O
Receive Positive Data. Positive pulse data output to the terminal equipment.
17
ICT
I
Output In-Circuit Test Control (Active-Low). If ICT is forced low, all digital
output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-
impedance state to allow for in-circuit testing.
18
REQB
I
Receive Equalization Bypass. A high on this pin bypasses the internal
equalizer. A low places the equalizer in the data path.
19
LOSTHR
I
Loss-of-Signal Threshold Control. The voltage forced on this pin controls the
input loss-of-signal threshold. Three settings are provided by forcing the GND,
V
DD/2, or VDD at LOSTHR.
20
V
DDA
5V Analog Supply (+/-10%).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7295AEIWTR-F | 功能描述:外圍驅(qū)動器與原件 - PCI E3 Line Receiver RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295AT | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/Sonet STS-1 Integrated Line Receiver |
| XRT7295AT_10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3 SONET STS1 Integrated Line Receiver |
| XRT7295ATIW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295ATIW-F | 功能描述:外圍驅(qū)動器與原件 - PCI -.5V--6.5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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