XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
á
PRELIMINARY
REV. P1.1.2
85
2.4.3.4
Register - 2 (E3, ITU-T G.832)
3.3.2.18 Receive E3 Interrupt Enable
Bit 6 - TTB Change Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Change in Trail Trace Buffer Message in-
terrupt. Setting this bit-field to "1" enables this inter-
rupt. Setting this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on Trail Trace Buffer mes-
sages, please see Section 5.3.2.9.
Bit 5 - Received LAPD Message Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Received LAPD Message frame interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on this interrupt, please see
Section 5.3.6.1.12.
Bit 4 - FEBE (Far-End Block Error) Interrupt En-
able
This Read/Write bit-field allows the user to enable or
disable the Far-End-Block Error (FEBE) interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on the FEBE Interrupt condi-
tion, please see Section 5.3.6.1.8.
Bit 3 - FERF (Far-End Receive Failure) Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Change in FERF Condition interrupt. Set-
ting this bit-field to "1" enables this interrupt. Setting
this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on the Change in FERF Condi-
tion interrupt, please see Section 5.3.6.1.7.
Bit 2 - EM Byte Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the EM Byte Error interrupt. Setting this bit-
field to "1" enables this interrupt. Setting this bit-field
to "0" disables this interrupt.
N
OTE
:
For more information on this interrupt, please see
Section 5.3.6.1.9.
Bit 1 - Framing Byte Error Interrupt Enable
This Read/Write bit-field allows the user to enable or
disable the Framing Byte Error interrupt. Setting this
bit-field to "1" enables this interrupt. Setting this bit-
field to "0" disables this interrupt.
N
OTE
:
For more information on this interrupt, please see
Section 5.3.6.1.10.
Bit 0 - Receive Payload Type Mismatch Interrupt
Enable
This Read/Write bit-field allows the user to enable or
disable the Receive Payload Type Mismatch interrupt.
Setting this bit-field to "1" enables this interrupt. Set-
ting this bit-field to "0" disables this interrupt.
N
OTE
:
For more information on this interrupt, please see
Section 5.3.6.1.11.
2.4.3.5
Receive E3 Interrupt Status Register -
1 (E3, ITU-T G.832)
RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Not Used
TTB
Change
Interrupt
Enable
Not Used
FEBE
Interrupt
Enable
FERF
Interrupt
Enable
BIP-8
Error Interrupt
Enable
Framing
Byte Error
Interrupt
Enable
RxPld
Mis
Interrupt
Enable
RO
R/W
RO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Not Used
SSM MSG
Interrupt
Status
SSM OOS
Interrupt
Status
COFA
Interrupt
Status
OOF
Interrupt
Status
LOF
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
RO
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0