參數(shù)資料
型號： XRT72L74
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 1/104頁
文件大?。?/td> 1301K
代理商： XRT72L74
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
á
PRELIMINARY
XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
DECEMBER 2000
REV. P1.0.0
GENERAL DESCRIPTION
The XRT72L74 Four Channel DS3 ATM User Net-
work Interface (UNI)/Clear Channel Framer is de-
signed to function as either a DS3 ATM UNI or Clear
channel framer. For ATM UNI applications, this de-
vice provides the ATM Physical Layer (Physical Medi-
um Dependent and Transmission Convergence sub-
layers) interface for both the public and private net-
works at DS3 rates. For Clear-Channel framer appli-
cations, this device supports the transmission and re-
ception of “user data” via the DS3 payload bits.
The XRT72L74 incorporates Receive, Transmit, Micro-
processor Interface, Performance Monitor, Test and Di-
agnostic and Line Interface Unit Scan Drive sections.
APPLICATIONS
Private User Network Interfaces
ATM Switches
ATM Concentrators
DSLAM Equipment
DS3 Frame Relay Equipment
FEATURES
Compliant with UTOPIA Level 1 and 2 with 8 or 16
Bit Interface Specification and supports UTOPIA
Bus speeds of up to 50 MHz
Contains on-chip 16 cell FIFO in both the Transmit
(TxFIFO) and Receive Directions (RxFIFO)
Contains on-chip 54 byte Transmit OAM Cell buffer
and a 108 byte Receive OAM cell buffer, for trans-
mission, reception and processing of OAM cells.
Supports PLCP or ATM Direct Mapping modes
Supports M13 and C-Bit Parity Framing Formats
Supports DS3 Clear Channel Framing Applications
Includes PRBS Generator and Receiver
Supports Local, Remote-Line, Cell, and PLCP
Loop-backs
Interfaces to 8 or 16 Bit wide Motorola and Intel μPs
Low power 3.3V, 5V input tolerant, CMOS
352 pin PBGA Package
1 and 3 channel versions also available
F
IGURE
1. XRT72L74 S
IMPLIFIED
B
LOCK
D
IAGRAM
WITH
S
YSTEM
I
NTERFACES
XRT73L04
RxUClav
DS3/E3 LIU
Host Mode
Tx1
Rx1
TPDATA
TNDATA
TCK
SDOO
SCLK
SDI
RPOS
RNEG
RCLK1
TxPOS
TxNEG
TCK
TxLev
DMO
LLOOP
TAOS
RxPOS
RxNEG
RxLineClk
UTOPIA BUS
Level 2
16
25, 33 or 50
MHz
Intel/Motorola
μ
P
Configuration, Control and Status Monitor
ATM Switch
D[15:0]
D[7:0]
A[10:9]
Channel
Select
4 WR_RW
RD_DS
RDY_DTCK
Address
XRT72L74
ATM
Layer
Processor
Tx
UTOPIA
Interface
Tx
Cell
Processor
Tx
PLCP
Processor
Tx
DS3
Framer
Performance
Monitor
Microprocessor
Interface
FEAC
Processor
LAPD
Transceiver
Rx
UTOPIA
Interface
Rx
DS3
Framer
Rx
PLCP
Processor
Rx
Cell
Processor
LIU
Interface
Drive
and
Scan
Rx2
Tx3
Rx3
Tx4
Rx4
DS3
44.736 MHz
75
coax
75
coax
A[8:0]
Address
5
16
TxUClav
1 of 4 Channels
5
4
4
4
Tx2
4
4
4
Ch 2
Ch 3
Ch 4
Req
Reset
CS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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