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XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.2
XVII
Figure 192. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the falling edge of RxLineClk .............................................................. 408
6.3.2 The Receive E3 Framer Block .............................................................................................................. 408
Figure 193. A Simple Illustration of the Receive E3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 409
Figure 194. The State Machine Diagram for the Receive E3 Framer E3 Frame Acquisition/Maintenance Al-
gorithm ................................................................................................................................................ 410
Figure 195. Illustration of the E3, ITU-T G.832 Framing Format ........................................................ 411
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................. 412
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 412
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................. 413
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................. 413
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 413
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
52) ................................... 414
PMON F
RAMING
B
IT
/B
YTE
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
53) .................................... 414
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 414
T
ABLE
86: T
HE
R
ELATIONSHIP
BETWEEN
THE
L
OGIC
S
TATE
OF
THE
R
X
OOF
AND
R
X
LOF
OUTPUT
PINS
,
AND
THE
F
RAMING
S
TATE
OF
THE
R
ECEIVE
E3 F
RAMER
BLOCK
............................................................................ 415
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 415
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................. 415
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 416
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 1 (A
DDRESS
= 0
X
14) ................................................................. 416
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 416
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 417
T
HE
M
AINTENANCE
AND
A
DAPTATION
(
MA
)
BYTE
FORMAT
....................................................................... 417
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
1 - (E3, ITU-T G.832) (A
DDRESS
= 0
X
10) ........................ 417
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 418
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 418
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 418
Figure 196. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with a correct EM Byte. ....................................................................................................... 419
Figure 197. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the FEBE bit (within the MA byte-field) set to “0” ......................................................... 419
Figure 198. Illustration of the Local Receive E3 Framer block, receiving an E3 Frame (from the Remote
Terminal) with an incorrect EM Byte. .................................................................................................. 420
Figure 199. Illustration of the Local Receive E3 Framer block, transmitting an E3 Frame (to the Remote
Terminal) with the FEBE bit (within the MA byte-field) set to “1” ......................................................... 421
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 421
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
54) ..................................................... 421
PMON P
ARITY
E
RROR
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
55) ...................................................... 422
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 422
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- MSB (A
DDRESS
= 0
X
56) ....................................................... 422
PMON FEBE E
VENT
C
OUNT
R
EGISTER
- LSB (A
DDRESS
= 0
X
57) ........................................................ 422
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 423
6.3.3 The Receive HDLC Controller Block ..................................................................................................... 423
Figure 200. LAPD Message Frame Format ....................................................................................... 424
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 425
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 425
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) .............................................................................. 425
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) .............................................................................. 426
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) .............................................................................. 426
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) .............................................................................. 427
R
X
E3 LAPD S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
19) .............................................................................. 427
T
ABLE
87: T
HE
R
ELATIONSHIP
BETWEEN
THE
C
ONTENTS
OF
R
X
LAPDT
YPE
[1:0]
BIT
-
FIELDS
AND
THE
PMDL M
ES
-
SAGE
T
YPE
/S
IZE
................................................................................................................................... 427