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參數(shù)資料
| 型號： | XRT7300IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, TQFP-44 |
| 文件頁數(shù)： | 32/55頁 |
| 文件大小： | 608K |
| 代理商： | XRT7300IV |
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XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
á
28
Design Considerations for E3 Applications or if
the Overall Cable Length is known
Figure 18 indicates the following:
A.
the length of cable between the Transmitting Ter-
minal and the Digital Cross-Connect system can
range between 0 and 450 feet and
B.
the length of cable between the Digital Cross-
Connect system and the Receive Terminal can
range between 0 and 450 feet.
The overall cable length between the Transmitting
Terminal and the Receiving Terminal can range be-
tween very short cable length (near 0 feet) up to 900
feet.
If during system installation the overall cable length is
known, then (to optimize the performance of the
XRT7300 in terms of receive jitter performance, etc.),
the Receive Equalizer should be enabled or disabled
based upon the following recommendations:
The Receive Equalizer should be turned ON if the
Receive Section is going to receive a line signal with
an overall cable length of 300 feet or greater. The
Receive Equalizer should be turned OFF if the Re-
ceive Section is going to receive a line signal over a
cable length of less than 300 feet.
N
OTES
:
1. If the Receive Equalizer block is turned ON (in a
given Receive Section that is receiving a line signal
over short cable length), there is the risk of over-
equalizing the received line signal which could
degrade performance by increasing the amount of
jitter that exists in the recovered data and clock sig-
nals or by creating bit-errors.
2. The Receive Equalizer has been designed to
counter the frequency-dependent cable loss that a
line signal experiences as it travels from the Trans-
mitting Terminal to the Receiving Terminal. How-
ever, Receive Equalizer was not designed to
counter flat loss where all of the Fourier frequency
components in the line signal are subject to the
same amount of attenuation. Flat loss is handled
by the AGC block.
The Receive Equalizer block can be disabled setting
the REQDIS input pin “High” when operating in the
Hardware Mode or writing a "1" to the REQDIS bit-
field in Command Register CR2 when operating the
XRT7300 in the HOST Mode.
3.3
After the incoming line signal has passed through the
Receive Equalizer it is routed to the Slicer block. The
purpose of the Slicer is to quantify a given bit-period
(or symbol) within the incoming line signal as either a
“1” or a “0”.
3.4
C
LOCK
R
ECOVERY
PLL
The output of the Slicer, which is now Dual-Rail digital
pulses, is routed to the Clock Recovery PLL. The
purpose of the Clock Recovery PLL is to track the in-
coming Dual-Rail data stream and to derive and gen-
erate a recovered clock signal.
It is important to note that the Clock Recovery PLL re-
quires a line rate clock signal at the EXCLK input pin.
The Clock Recovery PLL operates in one of two
modes:
The Training Mode.
The Data/Clock Recovery Mode
1. The Training Mode
If the XRT7300 is not receiving a line signal via the
RTIP and RRING input pins or if the frequency differ-
ence between the line signal and that applied via the
EXCLK input pin exceeds 0.5%, then the XRT7300
LIU IC is operating in the Training Mode. When the
LIU is operating in the Training Mode it does the fol-
lowing:
A.
declares a Loss of Lock indication by toggling the
RLOL output pin “High” and
B.
outputs a clock signal via the RCLK1 and RCLK2
output pins which is derived from the signal ap-
plied to the EXCLK input pin.
2. The Data/Clock Recovery Mode
If the frequency difference between the line signal
and that applied via the EXCLK input pin is less than
0.5%, the XRT7300 LIU IC is operating in the Data/
Clock Recovery Mode. In this mode, the Clock Re-
covery PLL is locked onto the line signal via the RTIP
and RRING input pins.
3.5
T
HE
HDB3/B3ZS D
ECODER
The Remote Transmitting Terminal typically encodes
the line signal into some sort of Zero Suppression
Line Code (e.g., HDB3 for E3 and B3ZS for DS3 and
STS-1). The purpose of this encoding activity was to
aid in the Clock Recovery process of this data in the
Near-End Receiving Terminal. However, once the da-
ta has made it across the E3, DS3 or STS-1 Trans-
port Medium and has been recovered by the Clock
Recovery PLL, it is now necessary to restore the orig-
inal content of the data. The purpose of the HDB3/
B3ZS Decoding block is to restore the data (transmit-
P
EAK
D
ETECTOR
AND
S
LICER
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
DECODIS ENCODIS ALOSDIS DLOSDIS
REQDIS
X
0
X
X
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRT7300IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7300IVTR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT7300IVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT7302IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| XRT73L00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
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