參數(shù)資料
型號(hào)： XRT7302
廠商： Exar Corporation
英文描述： 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
中文描述： 2頻道E3/DS3/STS-1線路接口單元（2通道E3/DS3/STS-1線接口單元）
文件頁(yè)數(shù)： 1/62頁(yè)
文件大?。?/td> 715K
代理商： XRT7302
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
á
XRT7302
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
SEPTEMBER 2000
REV. 1.1.6
GENERAL DESCRIPTION
The XRT7302 Dual Channel E3/DS3/STS-1 Trans-
ceiver IC consists of two fully integrated transmitter
and receiver line transceivers designed for E3, DS3
or SONET STS-1 applications.
Each channel can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates. Each channel can be con-
figured to operate in a mode/data rate that is indepen-
dent of the other channel.
In the transmit direction, each channel in the
XRT7302 encodes input data to either B3ZS or HDB3
format and converts the data into the appropriate
pulse shapes for transmission over coaxial cable via a
1:1 transformer.
In the receive direction, the XRT7302 can perform
Equalization on incoming signals, perform Clock Re-
covery, decode data from either B3ZS or HDB3 for-
mat, convert the receive data into TTL/CMOS format,
check for LOS or LOL conditions and detect and de-
clare the occurrence of Line Code Violations.
FEATURES
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Single +5V Power Supply
Uses Minimum External components
Operates over -40°C to +85°C Temperature Range
Available in an 80 pin TQFP Thermal Enhanced
package with integral Heat Sink
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
XRT7302 BLOCK DIAGRAM
AGC/
Equalizer
Serial
Processor
Interface
Peak Detector
LOS Detector
Pulse
Shaping
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
SDI
SDO
SClk
CS
REGR
TTIP(n)
TRing(n)
RTIP(n)
RRing(n)
REQEN(n)
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
E3_Ch(n) STS-1/DS3_Ch(n) Host/HW RLOL(n) ExClk(n) RxClkINV
Channel 0
Channel 1
Device
Monitor
Tx
Control
TxLEV(n)
TxOFF(n)
DMO(n)
MTIP(n)
MRing(n)
ENDECDIS
Notes: 1. (n) = 0 or 1 for the respective channel.
2. Serial Processor Interface pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode.
LOSTHR(n)
RxOFF(n)
相關(guān)PDF資料
PDF描述
XRT73L02M TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02MIV TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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