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參數(shù)資料
| 型號： | XRT7302IV |
| 英文描述： | PCM Transceiver |
| 中文描述： | 收發(fā)器的PCM |
| 文件頁數(shù)： | 10/53頁 |
| 文件大?。?/td> | 604K |
| 代理商： | XRT7302IV |
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XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
á
7
22
CS/(DR/SR)
I
Microprocessor Serial Interface - Chip Select/Encoder and Decoder Dis-
able
The function of this input pin depends upon whether the XRT73L00 is operating
in the HOST or the Hardware Mode.
HOST Mode - Chip Select Input:
The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to
enable communication with the XRT73L00 via the Microprocessor Serial Inter-
face.
Hardware Mode - Dual-Rail/Single-Rail Select Input:
Setting this input pin “High” configures the XRT73L00 to operate in the Dual-Rail
Mode. When the XRT73L00 is operating in this mode, then the Receive Section
of the LIU IC outputs the Recovered Data via both RPOS and RNEG output pins.
Setting this input pin “Low” configures the XRT73L00 to operate in the Single-
Rail Mode. When the XRT73L00 is operating in this mode, the Receive Section
of the LIU IC outputs the Recovered Data via the RPOS output pin in a binary
data stream. No data will output via the RNEG output pin.
23
RLOL
O
Receive Loss of Lock Output Indicator
This output pin toggles “High” if the XRT73L00 has detected a Loss of Lock Con-
dition. The XRT73L00 declares an LOL (Loss of Lock) Condition if the recovered
clock frequency deviates from the Reference Clock frequency (available at the
EXCLK input pin) by more than 0.5%.
N
OTE
:
The RCLK1/2 output pins are sourced by the signal applied at the EXCLK
input pin anytime the XRT73L00 declares an LOL condition.
24
RLOS
O
Receive Loss of Signal Output Indicator
This output pin toggles “High” if the XRT73L00 has detected a Loss of Signal
Condition in the incoming line signal.
The criteria the XRT73L00 uses to declare an LOS Condition depends upon
whether the device is operating in the E3 or DS3/STS-1 Mode.
25
DGND
****
Digital Ground
26
DVDD
****
Digital Power Supply
27
EXCLK
I
External Reference Clock Input:
Apply a line-rate clock signal to this input pin. This signal is a 34.368MHz clock
signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a
51.84 MHz clock signal for SONET STS-1 applications.
N
OTE
:
This input pin functions as the source of the RxCLK output clock signal
any time the XRT73L00 declares an LOL condition.
28
RxDGND
****
Receiver Digital Ground
29
RxDVDD
****
Receiver Digital Power Supply
PIN DESCRIPTION
P
IN
#
S
YMBOL
T
YPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L03 | 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73L03IV | 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73LC00 | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC00IV | E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00 | E3/DS3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00A | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00AES | 功能描述:界面開發(fā)工具 Eval System for XRT73L00A Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XRT73L00AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE INTERFACE|QFP|44PIN|PLASTIC |
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