
á
XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
32
3.5.2
If the XRT73L00 is configured to operate in the E3
Mode, the HDB3/B3ZS Decoding Block performs
HDB3 Decoding. When the Decoder is operating in
this mode it parses through the incoming Dual-Rail
data and checks for the occurrence of either a “000V”
HDB3 Decoding E3 Applications
or a “B00V” pattern. If the HDB3 Decoder detects
this particular pattern, it substitutes these bits with a
“0000” pattern.
Figure 20 illustrates the HDB3 Decoder at work with
two separate Zero Suppression patterns in the in-
coming Dual-Rail Data Stream.
N
OTE
:
If the HDB3 Decoder detects any bipolar violation
(e.g., “V”) pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) “0’s” in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High”.
3.5.3
Enabling/Disabling the HDB3/B3ZS
Decoder
The HDB3/B3ZS Decoder of the XRT73L00 can be
enabled or disabled by either of the following means:
If the XRT73L00 is operating in the Hardware
Mode:
Enable the HDB3/B3ZS Encoder/Decoder by pulling
the ENDECDIS input pin (pin 21) to GND. To disable
the HDB3/B3ZS Encoder/Decoder, pull the ENDEC-
DIS input pin to VDD.
If the XRT73L00 is operating in the HOST Mode:
Enable the XRT73L00 HDB3/B3ZS Encoder/Decoder
by writing a “0” into the ENDECDIS bit-field in Com-
mand Register CR2. To disable the HDB3/B3ZS En-
F
IGURE
19. A
N
E
XAMPLE
OF
B3ZS D
ECODING
Data
0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
RPOS
RNEG
0 0 V
Line Signal
B 0 V
RCLK
F
IGURE
20. A
N
E
XAMPLE
OF
HDB3 D
ECODING
Data
0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1
0 0 0 V
Line Signal
B 0 0 V
RPOS
RNEG
RCLK