參數(shù)資料
型號(hào)： XRT7302IV
英文描述： PCM Transceiver
中文描述： 收發(fā)器的PCM
文件頁(yè)數(shù)： 8/53頁(yè)
文件大?。?/td> 604K
代理商： XRT7302IV
XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
á
5
15
RLB
I
Remote Loop-Back Select:
This input pin along with LLB dictates which Loop-Back mode the XRT73L00 is
be operating in.
A “High” on this pin with LLB being set to “Low” configures the XRT73L00 to
operate in the Remote Loop-Back Mode.
A “High” on this pin with LLB also being set to “High” configures the XRT73L00
to operate in the Digital Local Loop-Back Mode.
N
OTES
:
1. This input pin is ignored if the XRT73L00 is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00 is going to be operating in the
HOST Mode.
16
STS-1/DS3
I
STS-1/DS3 Select Input:
A “High” on this pin configures the Clock Recovery Phase Locked Loop to set its
VCO Center frequency to around 51.84 MHz for SONET STS-1 operations. A
“Low” on this pin configures the Clock Recovery Phase Locked Loop to set its
VCO Center frequency to around 44.736 MHz for DS3 operations.
N
OTES
:
1. The XRT73L00 ignores this pin if the E3 pin (pin 17) is set to “1”.
2. This input pin is ignored if the XRT73L00 is operating in the HOST
Mode.
3. Tie this pin to GND if the XRT73L00 is going to be operating in the
HOST Mode.
17
E3
I
E3 Select Input:
A “High” on this pin configures the XRT73L00 to operate in the E3 Mode.
A “Low” on this pin configures the XRT73L00 to check the state of the STS-1/
DS3 input pin.
N
OTES
:
1. This input pin is ignored if the XRT73L00 is operating in the HOST
Mode.
2. Tie this pin to GND if the XRT73L00 is going to be operating in the
HOST Mode.
18
HOST/HW
I
HOST/HW Mode Select:
This input pin is used to enable or disable the Microprocessor Serial Interface
(e.g., consisting of the SDI, SDO, SCLK, CS and REGRESET pins).
Setting this input pin “High” enables the Microprocessor Serial Interface (e.g.
configures the XRT73L00 to operate in the HOST Mode). In this mode, the
XRT73L00 is configured by writing data into the on-chip Command Registers via
the Microprocessor Serial Interface. When the XRT73L00 is operating in the
HOST Mode, it ignores the states of many of the discrete input pins.
Setting this input pin “Low” disables the Microprocessor Serial Interface (e.g.,
configures the XRT73L00 to operate in the Hardware Mode). In this mode, many
of the external input control pins are functional.
PIN DESCRIPTION
P
IN
#
S
YMBOL
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT
XRT73L03IV 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT
XRT73LC00 E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73LC00IV E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L00 E3/DS3/STS-1 LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT73L00 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L00A 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L00AES 功能描述:界面開發(fā)工具 Eval System for XRT73L00A Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XRT73L00AIV 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L00IV 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE INTERFACE|QFP|44PIN|PLASTIC
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