參數(shù)資料
型號(hào)： XRT73L02MIV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-100
文件頁(yè)數(shù)： 35/46頁(yè)
文件大小： 391K
代理商： XRT73L02MIV
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XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
There are two distinct characteristics of jitter transfer: i) jitter gain (jitter peaking) defined as the highest ratio
above 0dB; and ii) jitter transfer bandwidth.The overall jitter transfer bandwidth is controlled by a low bandwidth
loop, typically using a voltage-controller crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter.
33
6.0.3
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and da-
ta recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is es-
sentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set ac-
cording to the data rate. In general, the jitter is measured over a band of frequencies.
J
ITTER
G
ENERATION
:
7.0
A serial microprocessor interface is included in the XRT73L02M. The interface is generic and is designed to
support the common microprocessors/microcontrollers. The XRT73L02M is configured in Host mode when the
HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input (SDI), serial
data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure
11.
The active low interrupt output signal (INT pin) indicates alarm conditions like LOS and DMO to the processor.
When configured in Host mode, the following input pins,TxLEV_n, TAOS_n, RLB_n, LLB_n, E3_n, STS-1/
DS3_n, REQEN_n are disabled and must be connected to ground.
SERIAL HOST INTERFACE:
The Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode.
N
OTE
:
While configured in Host mode, the TxON input pin will be active if the TxON_n bits in the control register are set to
“1”, and can be used to turn on and off the transmit output drivers. This permits a system designed for redundancy to
quickly switch out a defective line card and switch-in the backup line card.
T
ABLE
12: F
UNCTIONS
OF
SHARED
PINS
P
IN
N
UMBER
I
N
H
OST
M
ODE
I
N
H
ARDWARE
M
ODE
29
CS
RxClkINV
30
SClk
TxClkINV
31
SDI
RxON
27
SDO
RxMON
28
INT
LOSMUT
T
ABLE
13: R
EGISTER
M
AP
AND
B
IT
N
AMES
A
DDRESS
(H
EX
)
P
ARAMETER
N
AME
D
ATA
B
ITS
7
6
5
4
3
2
1
0
0x00
APS/Redundancy
(read/write)
Reserved
RxON-1
RxON_0
Reserved
TxON-1
TxON_0
相關(guān)PDF資料
PDF描述
XRT73L02 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線接口單元)
XRT73L03A 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03BIV 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT73L02MIV-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT73L02MIVTR-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT73L03 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT
XRT73L03A 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
XRT73L03AIV 制造商:Exar Corporation 功能描述:
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