XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
6
RECEIVE INTERFACE
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
59
53
121
127
RxClk_0
RxClk_1
RxClk_2
RxClk_3
O
R
eceive Clock Output - Channel (n):
This output pin is the Recovered Clock signal from the incoming line sig-
nal for Channel (n). The Receive Section of Channel (n) outputs data via
the RPOS_(n) and RNEG_(n) output pins on the rising edge of this clock
signal.
Configure the Receive Section of Channel (n) to update the data on the
RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n)
by doing one of the following:
a.
Operating in the Hardware Mode
Pull the RxClkINV pin to "High".
b.
Operating in the HOST Mode
Write a "1" into the RxClkINV bit-field within the Command Register.
60
54
120
126
RNEG_0/LCV_0
RNEG_1/LCV_1
RNEG_2/LCV_2
RNEG_3/LCV_3
O
Receive Negative Data Output - Channel (n):
The function of this pin is dependent on whether the 73L04A is in the
Hardware or HOST Mode (HOST/HW) and the condition of CS/(SR/DR).
a.
Operating in the Hardware Mode
Receive Negative Data:
Setting the CS/(SR/DR
) pin ”Low”, (Dual-Rail operation) this output pin
pulses "High" whenever Channel (n) has received a Negative Polarity
pulse in the incoming line signal at the RTIP_(n) and RRing_(n) inputs.
Line Code Violation:
When CS/(SR/DR) is set “High”, (Single-Rail operation), the B3ZS/HDB3
Encoder/Decoder is activated and the Line Code Violation signal is out-
put on this pin.
b.
Operating in the HOST Mode
Receive Negative Data:
Writing a “0” to the (SR/DR)_(n) bit in the command register configures
channel(n) in the Dual-Rail Mode and activates RNEG_(n).
Writing a “1” to (SR/DR)_(n) bit of the Command Register configures the
Single-Rail Mode and activates LCV_(n).
If the B3ZS/HDB3 Decoder is enabled then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V")
is not reflected at this output.
61
55
119
125
RPOS_0
RPOS_1
RPOS_2
RPOS_3
O
Receive Positive Data Output - Channel (n):
The function of this pin is dependent on the setting of the CS/(SR/DR)
pin.
Receive Positive Data
If CS/(SR/DR) is set “Low” (Dual-Rail Mode), this output pin pulses
"High" whenever Channel (n) has received a Positive Polarity pulse in
the incoming line signal at the RTIP_(n)/RRing_(n) inputs.
Data Output
If CS/(SR/DR) is set “High” (Single-Rail Mode), data is output on this pin.
If the B3ZS/HDB3 Decoder is enabled then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V")
is not reflected at this output.
79
87
102
94
RRing_0
RRing_1
RRing_2
RRing_3
I
Receive Ring Input - Channel (n):
This input pin along with RTIP_(n) is used to receive the bipolar line sig-
nal from the Remote DS3/E3/STS-1 Terminal.