參數(shù)資料
型號: XRT73L04AIV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, HEAT SINK, TQFP-144
文件頁數(shù): 7/65頁
文件大?。?/td> 366K
代理商: XRT73L04AIV
XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
IV
Figure 34. A channel operating in the Analog Local Loop-Back Mode ........................................................... 48
4.2 T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
. ......................................................................................... 49
C
OMMAND
R
EGISTER
CR4-(
N
) ............................................................................................................ 49
Figure 35.The Digital Local Loop-Back path within a given channel .............................................................. 49
C
OMMAND
R
EGISTER
CR4-(
N
) ............................................................................................................ 49
4.3 T
HE
R
EMOTE
L
OOP
-B
ACK
M
ODE
................................................................................................... 50
Figure 36.The Remote Loop-Back path, within a given channel .................................................................... 50
C
OMMAND
R
EGISTER
CR4-(
n
) ............................................................................................................ 50
4.4 T
X
OFF F
EATURES
......................................................................................................................... 51
C
OMMAND
R
EGISTER
CR1-(
N
) ............................................................................................................ 51
Table 6:The Relationship Between the TxOFF Input Pin, the TxOFF Bit Field and the State of the Transmitter
51
4.5 T
HE
T
RANSMIT
D
RIVE
M
ONITOR
F
EATURES
.................................................................................... 51
Figure 37.The XRT73L04A employing the Transmit Drive Monitor Features ................................................. 52
4.6 T
HE
TAOS (T
RANSMIT
A
LL
O
NE
S) F
EATURE
................................................................................. 52
5.0 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 52
5.1 D
ESCRIPTION
OF
THE
C
OMMAND
R
EGISTERS
.................................................................................. 52
C
OMMAND
R
EGISTER
CR1-(
N
) ............................................................................................................ 52
Table 7:Hexadecimal Addresses and Bit Formats of XRT73L04A Command Registers ............................... 53
5.2 D
ESCRIPTION
OF
B
IT
-F
IELDS
FOR
EACH
C
OMMAND
R
EGISTER
......................................................... 54
Command Register - CR0-(n) ............................................................................................................ 54
C
OMMAND
R
EGISTER
CR
0-(
N
) ............................................................................................................. 54
C
OMMAND
R
EGISTER
CR1-(
N
) ............................................................................................................ 55
Command Register CR2-(n) .............................................................................................................. 55
C
OMMAND
R
EGISTER
CR2-(
N
) ............................................................................................................ 55
C
OMMAND
R
EGISTER
CR3-(
N
) ............................................................................................................ 56
C
OMMAND
R
EGISTER
CR4-(
N
) ............................................................................................................ 57
Table 8:Contents of LLB_(n) and RLB_(n) and the Corresponding Loop-Back Mode for Channel(n) ........... 57
5.3 O
PERATING
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
. ................................................................. 57
Figure 38.Microprocessor Serial Interface Data Structure ............................................................................. 58
Figure 39.Timing Diagram for the Microprocessor Serial Interface ................................................................ 59
O
RDERING
INFORMATION
..................................................................................................... 60
P
ACKAGE
D
IMENSIONS
........................................................................................................ 60
R
EVISION
H
ISTORY
..................................................................................................................................... 61
R
EV
# ................................................................................................................................................ 61
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