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參數(shù)資料
| 型號： | XRT73LC00AIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 60/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU STS1/DS3/E3 SGL 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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XRT73LC00A
5
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
11
REGRESET/
(RCLK2INV)
I
Register Reset Input pin (Invert RCLK2 Output - Select):
The function of this pin depends upon whether the XRT73LC00A is operating in
the HOST Mode or in the Hardware Mode.
HOST Mode - Register Reset Input pin:
Setting this input pin “Low” causes the XRT73LC00A to reset the contents of the
Command Registers to their default settings and operating configuration. This
pin is internally pulled “High”.
Hardware Mode - Invert RCLK2 Output Select:
Setting this input pin “Low” configures the Receive Section of the XRT73LC00A
to output the recovered data via the RPOS and RNEG output pins on the rising
edge of the RCLK2 output signal.
Setting this input pin “High” configures the Receive Section to output the recov-
ered data on the falling edge of the RCLK2 output signal.
12
REQDIS
I
Receive Equalization Disable Input:
Setting this input pin “High” disables the Internal Receive Equalizer in the
XRT73LC00A. Setting this pin “Low” enables the Internal Receive Equalizer.
The guidelines for enabling and disabling the Receive Equalizer are described in
NOTES:
1.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
13
LOSTHR
I
Loss of Signal Threshold Control:
This input pin is used to select the LOS (Loss of Signal) Declaration and Clear-
ance thresholds for the Analog LOS Detector circuit. Two settings are provided
by forcing this signal to either GND or VDD.
NOTE: This pin is only applicable during DS3 or STS-1 operations.
14
LLB
I
Local Loop-Back Select:
This input pin along with RLB dictates which Loop-Back mode the XRT73LC00A
is operating in.
A “High” on this pin with RLB being set to “Low” configures the XRT73LC00A to
operate in the Analog Local Loop-Back Mode.
A “High” on this pin with RLB also being set to “High” configures the
XRT73LC00A to operate in the Digital Local Loop-Back Mode.
NOTES:
1.
This input pin is ignored if the XRT73LC00A is operating in the HOST
Mode.
2.
Tie this pin to GND if the XRT73LC00A is going to be operating in the
HOST Mode.
PIN DESCRIPTION
PIN #SYMBOL
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73LC03AIV-F | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| XRT73LC04AIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| XRT73R06IB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
| XRT73R12IB-L | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| XRT75L00DIV-F | IC LIU E3/DS3/STS-1 SGL 52TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC00AIVTR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00AIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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