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| 型號(hào)： | XRT73R06 |
| 廠商： | Exar Corporation |
| 英文描述： | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | 六通道線路接口單元E3/DS3/STS-1 |
| 文件頁(yè)數(shù)： | 40/68頁(yè) |
| 文件大小： | 347K |
| 代理商： | XRT73R06 |
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XRT73R06
REV. 1.0.0
á
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
37
5.0
There are three fundamental parameters that describe circuit performance relative to jitter
Jitter Tolerance
Jitter Transfer
Jitter Generation
5.1
J
ITTER
T
OLERANCE
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 26, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence. Input jitter tolerance requirements are specified in terms of
compliance with jitter mask which is represented as a combination of points. Each point corresponds to a
minimum amplitude of sinusoidal jitter at a given jitter frequency.
JITTER
5.1.1
Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II.
The jitter tolerance requirement for Category II is the most stringent. Figure 27 shows the jitter tolerance curve
as per GR-499 specification.
DS3/STS-1 Jitter Tolerance Requirements
F
IGURE
26. J
ITTER
T
OLERANCE
M
EASUREMENTS
FREQ
Synthesizer
Pattern
Generator
DUT
XRT73R06
Error
Detector
Modulation
Freq.
Data
Clock
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