參數(shù)資料
型號(hào): XRT73R06
廠(chǎng)商: Exar Corporation
英文描述: SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: 六通道線(xiàn)路接口單元E3/DS3/STS-1
文件頁(yè)數(shù): 59/68頁(yè)
文件大?。?/td> 347K
代理商: XRT73R06
á
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73R06
REV. 1.0.0
56
0x03 (ch 0)
0x13 (ch 1)
0x23 (ch 2)
0x33 (ch 3)
0x43 (ch 4)
0x53 (ch 5)
Read
Only
Alarm Sta-
tus
D0
DMO_n
This bit is set when no transitions on the TTIP/
TRING have been detected for 128 ± 32 TxCLK
periods.It will be cleared when pulses resume.
0
D1
RLOS_n
This bit is set every time the receiver declares an
LOS condition.It will be cleared when the signal is
recognized again.
0
D2
RLOL_n
This bit is set when the detected clock is greater
than 0.5% oof frequency from the reference clock.By
definition, the two frequencies are “not in lock” with
each other. It will be cleared when they are “in lock”
again..
0
D3
Reserved
This bit is Reserved.
0
D4
ALOS_n
This bit is set when the receiver declares that the
Analog signal has degraded to the point that the sig-
nal has been lost.
0
D5
DLOS_n
This bit is set when no input signals have been
received for 10 to 255 bit times in E3 or 100 to 250
bit times in DS3 or STS-1 modes.This is a complete
lack of incoming pulses rather than signal attenua-
tion (ALOS). It should be noted that this time period
is built into the Analog detector for E3 mode. Even
though DS3/STS-1 mode does not require analog
detection level, but it is provided and could help to
determine the “quality of the line” for DS/STS-1
applications.
0
D6
PRBSLS_n This bit is set when the PRBS detector has been
enabled and it is not in sync with the incoming data
pattern. Once the sync is achieved, it will be cleared.
0
D7
Reserved
T
ABLE
18: R
EGISTER
M
AP
D
ESCRIPTION
- C
HANNEL
N
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
BIT#
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
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