參數(shù)資料
型號(hào): XRT75L02
廠商: Exar Corporation
英文描述: TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
中文描述: 雙通道E3/DS3/STS-1線路接口單元,其抖動(dòng)
文件頁(yè)數(shù): 33/50頁(yè)
文件大?。?/td> 343K
代理商: XRT75L02
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
31
6.0
There are three fundamental parameters that describe circuit performance relative to jitter:
Jitter Tolerance (Receiver)
Jitter Transfer (Receiver/Transmitter)
Jitter Generation
6.1
J
ITTER
T
OLERANCE
- R
ECEIVER
:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence.
JITTER:
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as
a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter
frequency.
6.1.1
DS3/STS-1 Jitter Tolerance Requirements:
Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for
Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22
shows the jitter tolerance curve as per GR-499 specification.
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
FREQ
Synthesizer
Pattern
Generator
DUT
XRT75L02
Error
Detector
Modulation
Freq.
Data
Clock
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XRT75L02IV 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER