參數(shù)資料
型號: XRT75L02IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
中文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù): 13/50頁
文件大?。?/td> 343K
代理商: XRT75L02IV
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
11
MODE SELECT
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
2
24
E3_0
E3_1
I
E3 Mode Select Input
A "High" on this pin configures in E3 mode.
A "Low" on this pin configures in either STS-1 or DS3 mode depending on the
settings on pins 3 and 23..
N
OTES
:
1.
This pin is internally pulled down
2.
This pin is ignored if configured to operate in HOST mode.
3
23
STS1/DS3 _0
STS1/DS3 _1
I
STS-1/DS3 Select Input
A “High” on these pins configures in STS-1 mode.
A “Low” on these pins configures in DS3 mode.
These pins are ignored if the E3_n pins are set to “High”.
N
OTES
:
1.
This pin is internally pulled down
2.
This pin is ignored if configured to operate in HOST mode.
26
HOST/HW
I
Host/Hardware Mode:
Tie this pin “High” to configure in Host mode and “Low” for Hardware mode.
100
SR/DR
I
Single-Rail/Dual-Rail Select:
Setting this “High” configures both the Transmitter and Receiver to operate in
Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In
Single-rail mode, TNEG_n pin should be grounded.
Setting this “Low” configures both the Transmitter and Receiver to operate in
Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
N
OTE
:
This pin is internally pulled down.
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
29
CS
RxCLKINV
I
Microprocessor Serial Interface - Chip Select
Tie this “Low” to enable the communication with the Microprocessor Serial Inter-
face.
N
OTE
:
If configured in Hardware Mode, this pin functions as RxClkINV.
30
SCLK
TxCLKINV
I
Serial Interface Clock Input
The data on the SDI pin is sampled on the rising edge of this signal. Addition-
ally, during Read operations the Microprocessor Serial Interface updates the
SDO output on the falling edge of this signal.
N
OTE
:
If configured in Hardware Mode, this pin functions as TxClkINV.
31
SDI
RxON
I
Serial Data Input:
Data is serially input through this pin.
The input data is sampled on the rising edge of the SClk. .
N
OTES
:
1.
This pin is internally pulled down
2.
If configured in Hardware Mode, this pin functions as RxON.
相關(guān)PDF資料
PDF描述
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04DIV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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