參數(shù)資料
型號: XRT75L02IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
中文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù): 45/50頁
文件大?。?/td> 343K
代理商: XRT75L02IV
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
43
8.2.2
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback
is selected, the transmit clock (TxClk_n) and transmit data inputs (TPOS_n & TNEG_n) are looped back and
output onto the RxClk_n, RPOS_n and RNEG_n pins as shown in Figure 27. The data presented on TxClk,
TPOS and TNEG are not output on the TTIP and TRING pins.This provides the capability to configure the
protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the
primary card.
DIGITAL LOOPBACK:
N
OTE
:
Signals on the RTIP_n and RRING_n pins are ignored during digital loop back.
8.2.3
With Remote loop back activated as shown in Figure 28, the receive data on RTIP and RRING is looped back
after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit
timing. The receive data is also output via the RPOS and RNEG pins.
During the remote loop back mode, if the jitter attenuator is selected in the transmit path, the receive data after
the Clock and Data Recovery Block is looped back to the transmit path and passed through the jitter attenuator
using RxClk as the transmit timing.
IREMOTE LOOPBACK:
N
OTE
:
Input signals on TxClk, TPOS and TNEG are ignored during Remote loop back.
F
IGURE
26. A
NALOG
L
OOPBACK
F
IGURE
27. D
IGITAL
L
OOPBACK
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or Transmit path
Tx
Rx
1
1
TRING
TTIP
RRING
RTIP
RPOS
RNEG
RCLK
TNDATA
TCLK
TPDATA
HDB3/B3ZS
ENCODER
HDB3/B3ZS
DECODER
J
A
J
A
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
1
if enabled
2
if enabled and selected in either Receive or Transmit path
Tx
Rx
1
1
相關PDF資料
PDF描述
XRT75L03D THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04D FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04DIV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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XRT75L04IV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
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