參數(shù)資料
型號(hào): XRT75L02IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
中文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-100
文件頁(yè)數(shù): 41/50頁(yè)
文件大?。?/td> 343K
代理商: XRT75L02IV
XRT75L02
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
xr
REV. 1.0.3
39
0x04 (ch 0)
0x0C (ch 1)
R/W
Transmit
Control
D0
TxLEV_n
Set this bit for cable length greater than 225
feet.
N
OTE
:
See section 4.03 for detailed description.
0
D1
TxClkINV_
n
Set this bit to sample the data on TPOS/TNEG pins
on the rising edge of TxClk.
0
D2
TAOS_n
Set this bit to send a continuous stream of marks (All
Ones) out at the TTIP and TRING pins.
0
D3
Reserved
D4
INSPRBS_
n
Setting this bit causes the PRBS generator to insert
a single-bit error onto the transmit PRBS data
stream.
N
OTE
:
PRBS Generator/Detector must be enabled
for this bit to have any effect.
0
D5
TxMON_n
Setting this bit causes the driver monitor its own
transmit driver. When the transmit failure is
detected, DMO output pin goes “High” and DMOIS
bit is set.
When this bit is “0”, MTIP and MRing are connected
to other transmit channel for monitoring.
0
D7-D6
Reserved
0x05 (Ch 0)
0x0D (Ch 1)
R/W
Receive
Control
D0
REQEN_n
Set this bit to enable the Receive Equalizer.
N
OTE
:
See section 5.01 for detailed description.
0
D1
RxMON_n
Set this bit to configure the Receiver in monitoring
mode. In this mode, the Receiver can monitor a sig-
nal at the RTIP/RRING pins that has be attenuated
up to 20dB flat loss. However, internal LOS circuitry
is suppressed and LOS will never assert nor LOS be
declared when operating under this mode.
0
D2
LOSMUT_
n
Setting this bit causes the RPOS/RNEG outputs to
“0” while the LOS condition is declared.
N
OTE
:
If the bit has ben set, it will remain set even
after LOS condition is cleared.
0
D3
RxClkINV_
n
Set this bit to configure the Receiver to output
RPOS/RNEG data on the falling edge of RxClk_0.
0
D4
ALOSDIS_
n
Set this bit to disable the ALOS detector.
0
D5
DLOSDIS_
n
Set this bit to disable the DLOS detector.
0
D7-D6
Reserved
T
ABLE
19: R
EGISTER
M
AP
D
ESCRIPTION
- C
HANNEL
0
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
BIT#
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
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