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XRT75L03D
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.0
78
TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05
Channel 1 Address Location = 0x0D
Channel 2 Address Location = 0x15
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Unused
Disable DLOS
Detector
Disable ALOS
Detector
RxCLKINV
LOSMUT
Enable
Receive
Monitor Mode
Enable
Receive
Equalizer
Enable
R/O
R/W
0
0000
000
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
7 - 6
Unused
R/O
0
5
Disable DLOS
Detector
R/W
0
Disable Digital LOS Detector - Channel_n:
This READ/WRITE bit-field is used to either enable or dis-
able the Digital LOS (Loss of Signal) Detector within
Channel_n, as described below.
0 - Enables the Digital LOS Detector within Channel_n.
NOTE: This is the default condition.
1 - Disables the Digital LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been
configured to operate in the DS3 or STS-1 Modes.
4
Disable ALOS
Detector
R/W
0
Disable Analog LOS Detector - Channel_n:
This READ/WRITE bit-field is used to either enable or dis-
able the Analog LOS (Loss of Signal) Detector within
Channel_n, as described below.
0 - Enables the Analog LOS Detector within Channel_n.
NOTE: This is the default condition.
1 - Disables the Analog LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been
configured to operate in the DS3 or STS-1 Modes.
3
RxCLKINV
R/W
0
Receive Clock Invert Select - Channel_n:
This READ/WRITE bit-field is used to select the edge of
the RCLK_n output that the Receive Section of Channel_n
will use to output the recovered data via the RPOS_n and
RNEG_n output pins, as described below.
0 - Configures the Receive Section (within the correspond-
ing channel) to output the recovered data via the RPOS_n
and RNEG_n output pins upon the rising edge of RCLK_n.
1 - Configures the Receive Section (within the correspond-
ing channel) to output the recovered data via the RPOS_n
and RNEG_n output pins upon the falling edge of RCLK_n.