參數(shù)資料
型號: XRT75L04IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
中文描述: DATACOM, PCM TRANSCEIVER, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, LQFP-176
文件頁數(shù): 15/57頁
文件大小: 345K
代理商: XRT75L04IV
XRT75L04
13
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
87
SDI
RxON
I
Serial Data Input:
Data is serially input through this pin.
The input data is sampled on the rising edge of the SClk pin (pin 88).
N
OTES
:
1.
This pin is internally pulled down
2.
If configured in Hardware Mode, this pin functions as RxON.
85
SDO
RxMON
I/O
Serial Data Output:
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data is updated on the falling edge of the SClk and this
pin is tri-stated upon completion of data transfer.
N
OTE
:
If configured in Hardware Mode, this pin functions as RxMON.
84
INT
LOSMUT
I/O
INTERRUPT Output:
This pin functions as Interrupt Output for Serial Interface. A transition to “Low”
indicates that an interrupt has been generated by the Serial Interface. The inter-
rupt function can be disabled by setting the interrupt enable bit to “0” in the
Channel Control Register.
N
OTES
:
1.
In Hardware mode, this pin functions as LOSMUT.
2.
This pin will remain asserted “Low” until the interrupt is serviced.
133
RESET
I
Register Reset:
Setting this input pin "Low" causes the XRT75L04 to reset the contents of the
Command Registers to their default settings and default operating configuration
N
OTE
:
This pin is internally pulled up.
JITTER ATTENUATOR INTERFACE
P
IN
#
S
IGNAL
N
AME
T
YPE
D
ESCRIPTION
154
JA1
I
Jitter Attenuator Select 1:
In Hardware Mode, this pin along with the pin JA0 configures the Jitter Attenua-
tor as shown in the table.
N
OTE
:
This pin is internally pulled down.
SERIAL MICROPROCESSOR INTERFACE
JA0
0
0
Mode
16 bit FIFO
32 bit FIFO
JA1
0
1
1
1
Disable Jitter
Attenuator
Disable Jitter
Attenuator
0
1
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